9.3.2 Configuration
| High-Speed Bus Matrix Initiator | Initiator ID |
|---|---|
| CM4CPU – Cortex-M4F Processor | 0 |
| CM4CC – Cortex M Cache Controller | 1 |
| DMA RD – DMA-Read | 2 |
| DMA-WR – DMA-Write | 3 |
|
DSU/ICD (Test mode only) – Device Service Unit/In-Chip Debugger | 4 |
| CRYPTO | 5 |
| High-Speed Bus Matrix Target | Target ID |
|---|---|
| SRAM1 – SRAM Port 1 | 0 |
| SRAM2 – SRAM Port 2 | 1 |
| SRAM3 – SRAM Port 3 | 2 |
| SRAM4 – SRAM Port 4 | 3 |
| PCHE – Prefetch Cache of CM4CC | 4 |
| PCHE – Prefetch Cache of Peripherals | 5 |
| PB-B-A – Peripheral Bridge A | 6 |
| PB-B-B – Peripheral Bridge B | 7 |
| PB-B-C – Peripheral Bridge C | 8 |
| PB-B-D – Peripheral Bridge D | 9 |
| QSPI – Quad SPI Interface | 10 |
| ROT – Root of Trust | 11 |
| CRYPTO | 12 |