36.6.1 Digital Comparator

The ADC module features digital comparators that can be used to monitor selected analog input conversion results and generate interrupts when a conversion result is within the user-specified limits. Conversion triggers are still required to initiate conversions. The comparison occurs automatically once the conversion is complete. This feature is enabled by setting the Digital Comparator Module Enable bit, ENDCMP (ADCCMPCONx[7]).

The user application makes use of an interrupt that is generated when the analog-to-digital conversion result is higher or lower than the specified high and low limit values in the ADCCMPx register. The high and low limit values are specified in the DCMPHI[15:0] bits (ADCCMPx[31:16]) and the DCMPLO[15:0] bits (ADCCMPx[15:0]).

The CMPEx bits (x = 0 through 11) in the ADCCMPENx registers are used to specify which analog inputs are monitored by the digital comparator (for 12 analog inputs, ANx, where x = 0 through 11). The ADCCMPCONx register specifies the comparison conditions that generates an interrupt, as follows:

When IEBTWN is ‘1’, an interrupt is generated when DCMPLO ≤ ADCDATA < DCMPHI
When IEHIHI is ‘1’, an interrupt is generated when DCMPHI ≤ ADCDATA
When IEHILO is ‘1’, an interrupt is generated when ADCDATA < DCMPHI
When IELOHI is ‘1’, an interrupt is generated when DCMPLO ≤ ADCDATA
When IELOLO is ‘1’, an interrupt is generated when ADCDATA < DCMPLO

The comparator event generation is illustrated in the following figure. When the ADC module generates a conversion result, the conversion result is provided to the comparator. The comparator uses the DIFFx and SIGNx bits of the ADCIMCONx register (depending on the analog input used) to determine the data format used and to appropriately select whether the comparison must be signed or unsigned. The global ADC setting, which is specified by the FRACT bit (ADCCON1[23]), is also used to set the fractional or integer format. The digital comparator compares the ADC result with the high and low limit values (depending on the selected comparison criteria) in the ADCCMPx register.

Depending on the comparator results, a digital comparator interrupt event may be generated. If a comparator event occurs, the Digital Comparator Interrupt Event Detected status bit, DCMPED (ADCCMPCONx[5]), is set, and the Analog Input Identification (ID) bits, AINID[4:0] (ADCCMPCONx[12:8]), are automatically updated so that the user application knows which analog input generated the interrupt event.

Note: The user software must format the values contained in the ADCCMPx registers to match the converted data format as either signed or unsigned and fractional or integer.