34.10.6 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register are also reflected in the Interrupt Enable Clear register (INTENCLR).
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
 ERROR  RXFFTXFE SBMB 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 7 – ERROR Error Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit sets the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0Error interrupt is disabled.
1Error interrupt is enabled.

Bit 4 – RXFF RX FIFO Full Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit sets the RX FIFO Full bit, which enables the RX FIFO Full interrupt.

ValueDescription
0The RX FIFO Full interrupt is disabled.
1The RX FIFO Full interrupt is enabled.

Bit 3 – TXFE TX FIFO Empty Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit sets the TX FIFO Empty bit, which enables the TX FIFO Empty interrupt.

ValueDescription
0The TX FIFO Empty interrupt is disabled.
1The TX FIFO Empty interrupt is enabled.

Bit 1 – SB Client on Bus Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit sets the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.

ValueDescription
0The Client on Bus interrupt is disabled.
1The Client on Bus interrupt is enabled.

Bit 0 – MB Host on Bus Interrupt Enable

Writing ‘0’ to this bit has no effect.

Writing ‘1’ to this bit sets the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.

ValueDescription
0The Host on Bus interrupt is disabled.
1The Host on Bus interrupt is enabled.