7.3 Page Write

A page write operation allows up to eight bytes to be written in the same write cycle, provided all bytes are in the same row (address bits A6 through A3 are the same) of the memory array. Partial page writes of less than eight bytes are allowed.

A page write is initiated the same way as a byte write, but the bus host does not send a Stop condition after the first data byte is clocked in. Instead, after the EEPROM Acknowledges receipt of the first data byte, the bus host can transmit up to an additional seven data bytes.

The EEPROM will respond with an ACK after each data byte is received. Once all data bytes have been sent, the device requires a Stop condition to begin the write cycle. However, since a Stop condition is defined as a null bit frame with SI/O pulled high, the host does not need to drive the SI/O line to accomplish this. If a Stop condition is sent at any other time, the write operation is aborted. After the Stop condition is complete, the internally self-timed write cycle will begin. The SI/O pin must be pulled high via the external pull-up resistor during the entire t_WR cycle. Thus, in a multi‑client environment, communication to other single-wire devices on the bus should not be attempted while any devices are in an internal write cycle. After the maximum t_WR time has elapsed, the host may begin a new bus transaction.

The lower three bits of the memory address are internally incremented following the receipt of each data byte. The higher order address bits are not incremented, and the device retains the memory page location. Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. When the incremented word address reaches the page boundary, the address counter will “roll over” to the beginning of the same page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become unintentionally altered.