7.4 Writing to the Security Register

The Security register supports bytes writes, page writes, and partial page writes in the upper 16 bytes (upper two pages of eight bytes each) of the region. Page writes and partial page writes in the Security register have the same page boundary restrictions and behavior requirements as they do in the EEPROM.

Upon receipt of the proper device address byte (with opcode of Bh specified) and memory address byte, the EEPROM will send a logic ‘0’ to signify an ACK. The device will then be ready to receive the first data byte.

Following receipt of the data byte, the EEPROM will respond with an ACK and the host can send up to an additional seven bytes if desired. The EEPROM will respond with an ACK after each data byte is successfully received. Once all of the data bytes have been sent, the device requires a Stop condition to begin the write cycle. However, since a Stop condition is defined as a null bit frame with SI/O pulled high, the host does not need to drive the SI/O line to accomplish this. After the Stop condition is complete, the EEPROM will enter an internally self-timed write cycle, which will complete within a time of tWR, while the data are being programmed into the nonvolatile EEPROM. The SI/O pin must be pulled high via the external pull-up resistor during the entire tWR cycle. Thus, in a multi-client environment, communication to other single-wire devices on the bus should not be attempted while any devices are in an internal write cycle. Figure 7-3 is included below as an example of a byte write operation in the Security register.

Figure 7-3. Byte Write in the Security Register
Note:
  1. x = Don’t Care values in the place of A7‑A5 as these bits fall outside the addressable range of the Security register.
  2. Any attempt to interrupt the internal write cycle by driving the SI/O line low may cause the byte being programmed to be corrupted. Other memory locations within the memory array will not be affected. Refer to Device Behavior During Internal Write Cycle for the behavior of the device while the write cycle is in progress. If the host must interrupt a write operation, the SI/O line must be driven low for tDSCHG, as noted in Interrupting the Device during an Active Operation.