7.2 Byte Write
The AT21CS01/AT21CS11 supports writing of a single 8-bit byte and requires a 7-bit memory word address to select which byte to write.
Upon receipt of the proper device address byte (with opcode of Ah) and
memory address byte, the EEPROM will send a logic ‘
0’ to signify an ACK.
The device will then be ready to receive the data byte. Following receipt of the complete
8-bit data byte, the EEPROM will respond with an ACK. A Stop condition must then occur;
however, since a Stop condition is defined as a null bit frame with SI/O pulled high, the
host does not need to drive the SI/O line to accomplish this. If a Stop condition is sent
at any other time, the write operation is aborted. After the Stop condition is complete,
the EEPROM will enter an internally self-timed write cycle, which will complete within a
time of tWR, while the data are being programmed into the
nonvolatile EEPROM. The SI/O pin must be pulled high via the external pull-up resistor
during the entire tWR cycle. Thus, in a multi-client environment, communication
to other single-wire devices on the bus should not be attempted while any devices are in an
internal write cycle. After the maximum tWR time has elapsed,
the host may begin a new bus transaction.Note: Any attempt to interrupt the internal
write cycle by driving the SI/O line low may cause the byte being programmed to be
corrupted. Other memory locations within the memory array will not be affected. Refer to
Device Behavior During Internal Write Cycle for the behavior of the device
while the write cycle is in progress. If the host must interrupt a write operation, the
SI/O line must be driven low for tDSCHG as noted in Interrupting the Device during an
Active Operation.
Note:
x = Don’t Care bit in
the place of A7 as this bit falls outside the 1-Kbit addressable range.