Jump to main content
25.9.8 DMA Interrupt Priority 1 Status
Register
Table 25-14. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: INTSTAT1 Offset: 0x20 Reset: 0x00000000 Property: PAC
Write-Protection
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHx DMA Channel Active Interrupt at Priority
1
On this page
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 – CHx DMA Channel Active Interrupt at Priority
1
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.