25.9.5 DMA Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Bit 0-1, 8-9, 17-16, 24-25: QOSn, Priority Group n [n=1,..,4] QOS control | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Bit 0-1, 8-9, 17-16, 24-25: QOSn, Priority Group n [n=1,..,4] QOS control | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Bit 0-1, 8-9, 17-16, 24-25: QOSn, Priority Group n [n=1,..,4] QOS control | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Bit 0-1, 8-9, 17-16, 24-25: QOSn, Priority Group n [n=1,..,4] QOS control | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – Bit 0-1, 8-9, 17-16, 24-25: QOSn, Priority Group n [n=1,..,4] QOS control DMA Channel Active Interrupt at Priority 4
Sets the Quality of service level for Channel Priority Group n. Setting this value affects arbitration within the device bus fabric. This value does not affect arbitration within the DMA.
| Value | Description |
|---|---|
| 0x0 | QoS level is 0 (lowest) |
| 0x1 | QoS level is 1 (lower) |
| 0x2 | QoS level is 2 (medium) |
| 0x3 | QoS level is 3 (high) |