25.8.4 Interrupts

Interrupt generation by the DMA occurs at a channel level. Within each channel there is a range of bits that can set an interrupt flag. These are:

  • Start Detected (SD): Stated Detect interrupt is set when a start trigger is detected for the channel
  • Block Transfer Abort (TA): When the channel receives an abort trigger as described in Abort Trigger Source, the TA bit is set. The CHCTRLAk.ENABLE bit is cleared and the FSM advances to a block transfer complete state.
  • Cell Transfer Complete (CC): The CC flag is set when a cell transfer is complete. A cell transfer completes each time CHXSIZk.CSZ bytes have been written to the destination. Also, set the CC bit when BC is set.
  • Block Transfer Complete (BC): Set the BC bit when a block transfer completes or is aborted. A block transfer completes when CHXSIZk.BLKSZ bytes have been written to the destination.
  • Block Transfer Half Complete (BH): Set the BH bit on the first clock cycle when CHSTBCk.BBTC > CHXSIZk.BLKSZ / 2. The user may clear BH any time after the DMA sets the bit. The DMA will not set BH again for the duration of the block transfer.
  • Linked List Complete (LL): Set the LL bit when LLEN=1 and the CHNXTk.NXT register value is 0xFFFF_FFFF (NULL). The DMA will also clear LLEN under this condition.
  • Read Error (RDE)
  • Write Error (WRE)