25.8.5 CRC and Checksum Engine

The CRC and IP Header Checksum datapaths are designed to process up to 64-bits of data in a single clock. The following figure shows an overview of the CRC/Checksum engine and data paths for 32-bits.

Figure 25-13. CRC Engine

Data entering the block will be reordered such that the CRC checksum calculated for a block is the same regardless of read address mode (byte mode, half-word mode, or word mode). This reordering is completely transparent to software and is independent from the BYTORD setting chosen by the user. Because the system is little endian, in order to get the same CRC result, read halfwords will be byte swapped, and read words will have bytes in reverse order.

IP Header Checksum Datapath

The following figure shows a representation of the checksum datapath. The datapath processes a word each cycle. Each time a channel is granted bus access, the lower 16 bits of the CRCDAT register is loaded into the checksum register using signal LOAD_REG. On loss of arbitration or the end of cell transfer, save the checksum result SUM_OUT[15:0] into the lower 16 bits of CRCDAT. Repeat the process each time the channel gains arbitration and completes a cell transfer.

Figure 25-14. IP Header Checksum Datapath

In word mode, the datapath splits the 32-bit word into two 16-bit words, sums them with the existing sum result (either previously loaded or calculated from the last data word). If the result is greater than 16-bits, the upper 16-bit is summed with the lower 16-bits and captured in the sum result register.

In half-word mode, half-words are added to the previous sum result. If the result is larger than 16-bits, the upper 16-bits are summed with the lower 16-bits and stored into the sum register.

In byte mode, bytes read from even address locations extended to 16-bits with 0’s and added to the previous sum result. Again, if the value is larger than 16-bits, the upper 16-bits are summed with the lower 16-bits and stored into the sum register. For bytes read from odd addresses, the byte is shifted left 8-bits (multiply by 2^8) and summed with the previous sum result. If the resulting sum is larger than 16-bits, the upper 16-bits are summed with the lower 16-bits and stored in the sum register.

At the end of a cell transfer the checksum is stored back into CRCDAT[15:0].