39.8.1 SMC Setup Register
This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SETUP |
| Offset: | 0x00 + n*0x04 [n=0..3] |
| Reset: | 0x01010101 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NCS RD SETUP[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NRD SETUP[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NCS WR SETUP[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NWE SETUP[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
Bits 29:24 – NCS RD SETUP[5:0] NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS RD SETUP[5] + NCS RD SETUP[4:0]) clock cycles
Bits 21:16 – NRD SETUP[5:0] NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD SETUP[5] + NRD SETUP[4:0]) clock cycles
Bits 13:8 – NCS WR SETUP[5:0] NCS Setup Length in WRITE Address
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS WR SETUP[5] + NCS WR SETUP[4:0]) clock cycles
Bits 5:0 – NWE SETUP[5:0] NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE SETUP[5] + NWE SETUP[4:0]) clock cycles