39.8.4 SMC Mode Register

This register can only be written if the WPEN bit is cleared in the SMC Write Protection Mode Register. The user must confirm the SMC configuration by writing any one of the SMC MODE registers.

Table 39-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	MODE
Offset:	0x0C + n*0x04 [n=0..3]
Reset:	0x00
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			PS[1:0]					PMEN
Access			R/W	R/W				R/W
Reset			0	0				0


Bit	23	22	21	20	19	18	17	16
				TDF MODE	TDF CYCLES[3:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
				DBW				BAT
Access				R/W				R/W
Reset				0				0


Bit	7	6	5	4	3	2	1	0
			EXNW MODE[1:0]				WRITE MODE	READ MODE
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0

Bits 29:28 – PS[1:0] Page Size

If page mode is enabled, this field indicates the size of the page in bytes.


Value	Name	Description
`o`	4 BYTE	4-byte page
`1`	8 BYTE	8-byte page
`2`	16 BYTE	16-byte page
`3`	32 BYTE	32-byte page

Bit 24 – PMEN Page Mode Enabled

Value	Description
0	Standard read is applied.
1	Asynchronous burst read in page mode is applied on the corresponding chip select.

Bit 20 – TDF MODE TDF, Data Float Time, Optimization

Value	Description
0	TDF optimization disabled-the number of TDF wait states is inserted before the next access begins.
1	TDF optimization enabled-the number of TDF wait states is optimized using the setup period of the next read/write access.

Bits 19:16 – TDF CYCLES[3:0] Data Float Time

This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF CYCLES period. The external bus cannot be used by another chip select during TDF CYCLES + 1 cycles. From 0 up to 15 TDF CYCLES can be set.

Bit 12 – DBW Data Bus Width


Value	Name	Description
`o`	8 BIT	8-bit Data Bus
`1`	16 BIT	16-bit Data Bus
`2`	32 BIT	32-but Data Bus
`3`	-	Reserved

Bit 8 – BAT Byte Access Type

This field is used only if DBW defines a 16-bit data bus.


Value	Name	Description
`o`	BYTE SELECT	Byte select access type: Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3 Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3
`1`	BYTE WRITE	Byte write access type: Write operation is controlled using NCS, NWR0, NWR1, NWR2,NWR3 Read operation is controlled using NCS and NRD

Bits 5:4 – EXNW MODE[1:0] NWAIT Mode

The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.


Value	Name	Description
`o`	DISABLED	Disabled-The NWAIT input signal is ignored on the corresponding chip select.
`1`	Reserved
`2`	FROZEN	Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
`3`	READY	Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.

Bit 1 – WRITE MODE Write Mode


Value	Name	Description
0	NCS_CTRL	Write operation controlled by NCS signal—If TDF optimization is enabled (TDF_MODE = 1), TDF wait states will be inserted after the setup of NCS.
1	NWE_CTRL	Write operation controlled by NWE signal—If TDF optimization is enabled (TDF_MODE = 1), TDF wait states will be inserted after the setup of NWE.

Bit 0 – READ MODE Read Mode


Value	Name	Description
0	NCS_CTRL	Read operation controlled by NCS signal If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. If TDF optimization is enabled (TDF_MODE = 1), TDF wait states are inserted after the setup of NCS.
1	NRD_CTRL	Read operation controlled by NRD signal If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. If TDF optimization is enabled (TDF_MODE = 1), TDF wait states are inserted after the setup of NRD.

PIC32CZ CA80/CA90 Family