29.7.5 Event Control

Note: This register is write protected and can only be written when CTRLA.ENABLE = 0.
Table 29-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Important: On devices with security attribution Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the Non-Secure accesses to an Enabled-Protected register as it will not be possible for the Non-Secure to configure it once this register is enabled by the Secure application. This will require some veneers to be implemented on Secure side.
Name: EVCTRL
Offset: 0x08
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
 EXTINTEO[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 EXTINTEO[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:0 – EXTINTEO[15:0] External Interrupt Event Output Enable

The bit x of EXTINTEO enables the event associated with the EIC_EXTINTx pin.
ValueDescription
0Event from pin EIC_EXTINTx is disabled.
1Event from pin EIC_EXTINTx is enabled and will be generated when EIC_EXTINTx pin matches the external interrupt sensing configuration.