18.6.5.1 PLL Basic Operation

PLL Initialization, Enabling, and Disabling

The PLL is enabled by writing a one to the Enable bit in the Control register (PLLCTRL.ENABLE). The PLL is disabled by writing a zero to PLLCTRL.ENABLE.

Important: If the PLL is active, the user must ensure that at no time do they violate the minimum or maximum frequency ranges specified for FPFD, FVCO , and FCLK_PLL. Failure to do destabilize the VCO and lead to unpredictable behavior. Therefore carefully select the order in which the user configures the various scaler values in the PLL based on the FCKR clock source frequencies used in the application.

PLL Reference selection

The PLL controller supports three independent sources of reference clock:

  • DFLL48M: The reference clock is provided by the DFLL48M.
  • XOSC: The reference clock is provided by the External Multipurpose Crystal Oscillator (XOSC).
  • GCLK_PLLn_REF: The reference clock “GCLK_PLLn_REF” is provided by the Generic Clock Controller.

The reference source can be selected by setting the REFSEL bits in the PLLCTRL register. The frequency of the reference must be comprised between 4 MHz and 48 MHz.

PLL settings

The frequency generated by the PLL is determined by the following control registers:

  • PLLREFDIV: The PLL reference frequency divider, 1 ≤ REFDIV ≤ 63
  • PLLFBDIV: The PLL Feed Back frequency divider, 21 ≤ FBDIV ≤ 1023
  • POSTDIV: The PLL output frequency divider, 1 ≤ POSTDIV ≤ 63

When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is given in the equation below:

Equation 18-2. FCLK_PLL
FCLK_PLL⁢⁢= (FCKR* (FBDIV/ (REFDIV*POSTDIV)))

Where,

FCLK_PLL is the frequency of the PLL output clock, FCKR is the frequency of the selected reference clock, REFDIV is the reference prescaler value, FBDIV is the loop divider value, and POSTDIV is the output prescaler value.

Note: FCLK_PLL must always remain between 12.7 MHz to 300 MHz while configuring the various stages of the PLL, hence the VCO does not become unstable and lead to unpredictable behavior.

Example:

The goal is to have FCLK_PLL = 300 MHz:

Given:

  • XOSC = 12 MHz = FCKR
  • If REFDIV = 2 then FPFD = (FCKR / 2) = 6 MHz
  • If FBDIV = 150 then FVCO = (FPDF * FBDIV) = (6 MHz * 150) = 900 MHz
  • Setting POSTDIV = 3 then gives FCLK_PLL = (FVCO / 3 ) = (900 MHz /3) = 300 MHz

The frequency after the reference divider (FPDF) is given by the formula:

  • FPFD = FCKR / REFDIV (must be between 4 MHz to 48 MHz)

The frequency of the Voltage Controlled Oscillator (VCO) giving the PLL oscillation is given by the formula:

  • FVCO = FCKR * (FBDIV / REFDIV) (must be between 800 MHz and 1600 MHz)
Note: FCKR , REFDIV and FBDIV must be selected to satisfy these conditions.
Note:
  1. The PLLREFDIV and PLLFBDIV registers are not write-protected by the PAC. Alternatively, they can be write protected by setting the control bit ( PLLCTRL.WRTLOCK). When the OSCCTRL is PAC write-protected, the user can still tune the PLL frequency when the PLLCTRL.WRTLOCK is cleared, or the user can also write-protect the PLLREFDIV and PLLFBDIV registers when the PLLCTRL.WRTLOCK is set.
  2. Each PLL has up to four outputs. Each output has an individual PLL output frequency divider POSTDIVn and an individual output control enable OUTENn with n=0..3. Depending on the selected REFDIV and the reference frequency, the user must set the Band Width selection bits (BWSEL) in the PLLCTRL register. Refer to the PLLCTRL.BWSEL definition in the “Register Description” section.

PLL Lock and Clock Generation

After the PLL oscillator is enabled, the PLL controller waits for the oscillator to issue a Lock status. The PLLLOCK bit in the status register (STATUS.PLLLOCK) will be set and the PLL controller issue the clock to the system (GCLK). The frequency of the PLL output clock CLK_PLL is stable when the STATUS.PLLLOCK bit is set. The PLL lock rising bit (PLLLOCKR) in the INTFLAG register is set when the STATUS.PLLLOCK rises.

Note: During each PLL start-up phase, the clock to the internal modules is not delivered as long as the first lock is not detected. When the lock is detected, the clock is released to the GCLK as long as requested. The PLL outputs whose OUTEN bit are set will start issuing a clock when the PLL LOCK status bit STATUS.PLLLOCK = 1 is set.

PLL Disabling

The PLL is disabled by writing a zero to PLLCTRL.ENABLE. Due to the synchronization of control and configuration registers, generation of internal timings to stop and power down properly the PLL, the PLL will be active for a few microseconds after CTRLA.ENABLE is cleared. The end of the PLL activity can be checked with the status lock bit STATUS.LOCK being ZERO. The PLL reference must not be stopped until the status lock bit STATUS.LOCK is read ZERO.

PLL Operation in Sleep Modes

The PLL will behave differently in different sleep modes, based on the settings of PLLCTRL.ONDEMAND and PLLCTRL.ENABLE. PLLCTRL.ONDEMAND must be written when PLLCTRL.ENABLE = 0. Otherwise, the write of this bit is ignored. If PLLCTRL.ENABLE = 0, the PLL will always be stopped. For PLLCTRL.ENABLE = 1, this table is valid:

Table 18-3. PLL Sleep Behavior
CPU ModeON DEMANDSleep Behavior of DFLL48M
Active or Idle0Always run
Active or Idle1Run if requested by a peripheral
Standby0Always run
Standby1Run if requested by a peripheral
Backup0Always OFF
Backup1Always OFF

PLL Reference Clock Switching

When a software operation requires reference clock switching, the normal operation is to disable the PLL, modify the PLLCTRL.REFCLK and PLLCTRL.BWSEL to select the desired reference source and activate the PLL again. The CLK_PLL output clock is ready when STATUS.PLLLOCK bit is set.

PLL Updates

It is important to note that when doing run time PLL updates that the user ALWAYS insures that for any PLL register update, the PLL does not exceed any of the electrical specs listed below to ensure continued stable PLL operation. Depending on the PLL input clock frequency selected therefore the user may have to choose a specific sequence, (i.e., order), of PLL register updates to maintain specification compliance throughout the PLL module logic.

  • FCKR = 4 MHz to 48 MHz
  • FPFD = 4 MHz and 48 MHz
  • FVCO = 800 MHz to 1.6 GHz
  • FCLK_PLL = 12.7 MHz to 300 MHz