18.6.5.2 Fractional Divider

The Fractional Frequency Divider divides the PLL0 VCO, FVCO0, clock output frequency by a ratio composed of an integer part and a reminder part. Only the PLL0 supplies the clocks to the fractional dividers. FRACDIV0 is fed by PLL0 output 0 (under control of PLL0POSTDIVA[0]) and FRACDIV1 is fed by PLL0 output 1 (under control of PLL0POSTDIVA[1]). The maximum fractional divider input frequency is 1.6 GHz. The divided frequency is given by the integer and reminder part of the divider, FRACDIV.INTDIV and FRACDIV.REMDIV. The resulting frequency FFRACDIV is calculated using the following equation:

Equation 18-3. Fractional Divider Frequency
F C L K _ P L L 0 _ F R C _ C L K O U T n ⁢ ⁢ =   ( F C L K _ P L L ⁢ /   ( 2 ⁢ *   ( I N T D I V ⁢ +   ( R E M D I V ⁢ /   512 ) ) ) )
Note: This is not a true fractional divider in the sense that the resulting frequency is actually an average over time that represents the fractional frequency except in the cases where FCLK_PLL0_FRC_CLKOUTn value corresponds to a whole integer value. For decimal fractional values, the fractional divider logic steals input FVCO PLL clock cycles to produce and average output frequency equivalent to the desired frequency. As a result, the final FCLK_PLL0_FRC_CLKOUTn output frequency will have jitter equivalent to:
  • If Reminder ≤ 0.5:
    • FCLK_PLL0_FRC_CLKOUTn Jitter = (Remainder / FVCO )
  • If Reminder > 0.5:
    • FCLK_PLL0_FRC_CLKOUTn Jitter = ((1-Remainder) / FVCO ))

Fractional Divider Operating mode

The Fractional Divider must be configured and enabled as shown in the following section.

Configure and Enable the PLL Output

  1. Configure the integer and reminder divider factors FRACDIV.INTDIV and FRACDIV.REMDIV. If the PLL is not locked, the FRACDIV register write is pending until the PLL deliver a clock after the lock. The pending status can be checked in the SYNCBUSY.FRACDIVn register bit. The FRACDIV register can still be modified if the source PLL enable bit is not set.
  2. Enable the PLL output.
  3. Check the PLL lock with the register bits STATUS.PLLnLOCKR or INTFLAG.PLLnLOCKR.
  4. Check the SYNCBUSY.FRACDIVn register bit. When this bit is low, the FRACDIV is delivering the divided PLL clock. The Fractional Divider values FRACDIV.INTDIV and FRACDIV.REMDIV can be changed when the divider is operating. But before, the user must ensure that the previous Fractional Divider values change is completed by checking the bit SYNCBUSY.FRACDIVn is low.
Note: After a system reset the Fractional Divider starts in a frozen state. If the Fractional Divider is operating or synchronizing the divider factors, it is requesting a clock to the PLL source. The FRACDIV will stay frozen until the PLL source delivers a clock, which is indicated by the status LOCK bit (STATUS.PLLLOCK) being high. After the PLL source delivers a clock, the FRACDIV is unfrozen. If the fractional Divider stops its operation (no more GCLK request and no more on-going synchronization), it will go back to a frozen state and request the PLL source clock until it is actually frozen. After the freeze the status bit STATUS.PLLLOCK will go low, at the condition no other PLL output is requested. The freeze/unfreeze process ensures the FRACDIV divides on a locked PLL clock.
Figure 18-3. Fractional Divider
Note:
  1. FCLK_PLLFRC0 = (FCLK_PLL0 / (2 x (INTDIV + (REMDIV / 512)))).
  2. The maximum permitted fractional output frequency, FCLK_PLLFRC0, must always be limited to 200MHz by the user.
  3. Setting both INTDIV and REMDIV = 0 will yield FCLK_PLLFRC0 = FCLK_PLL0 which effectively bypasses the fractional divider module in which case the user must limit the output of PLL0 to the fractional divider module to FPLL0 = FCLK_PLL0 = 200MHz max.