31.2.9 Clocks

The FCW peripheral bus clock (CLK_FCW_APB) can be enabled and disabled in the Main Clock Controller.

The FCW data bus clock (CLK_FCW_AHB) can be enabled and disabled in the Main Clock Controller.

The FCW also requires an on-chip 8 MHz clock source that is automatically configured without application assistance. The CLK_GEN_FCW is derived by dividing the 48 MHz trimmed internal RC oscillator by 6.