31.2.20 Interrupts

The FCW has two sets of interrupts, which are serviced by the FCW interrupt vector. The main set of INTENCLR, INTENSET, and INTFLAG are for the system CPU.

The module has an interrupt output for CPU initiated NVMOPs that is controlled by INTENSET and INTENCLR. The interrupt status is reported via INTFLAG. A read of either INTENSET or INTENCLR returns the enable state for the specific interrupt condition. The Flash interrupt is asserted if a condition is enabled and its associated bit is set in INTFLAG. Interrupt flags are cleared by writing a 1 to its bit position in the INTFLAG register.

It is recommended to always enable DONE as interrupt source in INTENSET. Using DONE masks side effects of WRERR, RSTERR, HTDPGM, BUSERR, and FIFOERR being set before the FCW has finished cleaning up after an error.

STATUS.BUSY indicates if the FCW is performing an operation (from the CPU). INTFLAG.DONE indicates that the FCW has completed an NVMOP for the CPU.

Note: The FCW does not clear DONE automatically. Also, DONE=1 does not prevent NVM operations. Therefore, software must clear DONE before the next NVM operation is started.