37.6 Functional Description

Important: Before attempting to initialize and enable either of the two USBs, the user must first enable the internal USBx regulator, SUPC.VREGCTRL.AVREGEN, and then wait a minimum of 55µs for internal power to stabilize before reading or writing any of the USBx registers.

The universal serial bus (USB) is an industry standard serial bus used to facilitate communication between a host and devices within a hierarchical system. In the PIC32CZ CA family of MCUs, the Hi-Speed USB module is connected to the ARM M-7 core via the advanced high-performance bus (AHB). The Hi-Speed USB module has a dedicated DMA host to transfer data between the USB port and system memory.

The Hi-Speed USB module has two main modes of operation: Device mode and Embedded Host mode.

Device Mode

In Device mode, the Hi-Speed USB module encodes, decodes, checks, and directs all USB packets sent and received. IN transactions are handled through the device’s TX FIFOs, OUT transactions are handled through its RX FIFOs. Control, Bulk, Isochronous and Interrupt transactions are also supported.

Embedded Host Mode

In Embedded Host mode, the way in which the Hi-Speed USB module behaves depends on whether it is linked up for point-to-point communications with another USB system or whether it is attached to a hub. When attached directly to a USB system operating as a Device, the module offers the range of capabilities needed to act as the host in point-to-point communications with this USB system. When attached through a USB hub, the Hi-Speed USB module can perform the functions required to act as the host for multiple USB Devices simultaneously.

When operating in Embedded Host mode and used for point-to-point communications with a single other USB device (which can be Hi-Speed, Full-Speed, or Low-Speed), the Hi-Speed USB module can support Control, Bulk, Isochronous or Interrupt transactions. IN transactions are handled through the RX FIFOs, OUT transactions are handled through the TX FIFOs. As well as encoding, decoding and checking the USB packets sent and received, the module will also automatically schedule Isochronous endpoints and Interrupt endpoints to perform one transaction every ‘n’ frames/micro-frames (or up to three transactions if the high-bandwidth option is selected), where ‘n’ represents the polling interval that has been programmed for the endpoint. The remaining bus bandwidth is shared equally between the Control and Bulk endpoints.

Embedded Host Mode Through a Hub

When attached to a single or multiple USB devices through a USB hub, the Hi-Speed USB module continues to offer the facilities previously mentioned, but it needs to be further configured for the following functional overlays:

  • The function address of the target device
  • The operating speed of the target device (so that the appropriate speed conversion can be carried out)
  • If the target device is a Full-Speed or Low-Speed device that is accessed through a Hi-Speed hub, the endpoint additionally needs to be configured with the function address and port number of the hub

Operation

The initial operating role of the Hi-Speed USB module (Embedded Host mode or Device mode) depends on orientation of the Micro-AB cable. The orientation of the Micro-AB cable determines the logic state of USBID input pin. The USBID low state indicates the connection of the Micro-A side of the Micro-AB cable and initial operation in the Embedded Host role. The USBID high state indicates the connection of the Micro-B side of the Micro-AB cable and initial operation in the Device role. The cable orientation state of USBID can be superseded using the IDOVEN and IDVAL bits of the CTRLA register.

The HOSTREQ bit is provided in the DEVCTL register of the Hi-Speed USB module which can trigger a Host Negotiation, requesting that the system currently operating in the Device role swap to the Embedded Host role during the next USB bus idle period. Information about the current operating role and current bus connection speed can be found in the DEVCTL register.

Note: See the latest version of the USB-IF document On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification for the powering and wake signaling requirements for operating in the USB environment.

FIFOs

The Hi-Speed USB module has 9kB of dedicated RAM that can be dynamically allocated between the endpoint FIFOs.

Dedicated DMA

The Hi-Speed USB module has a dedicated, 8-channel DMA controller that can be set up to load/unload the endpoint FIFOs. Each of the DMA channels can be configured to operate in one of two modes:

  • DMA Mode 0: Allows one packet to be automatically transferred to/from its respective endpoint FIFO
  • DMA Mode 1: Allows for a complete Bulk transfer to be setup and automatically transferred to/from its respective endpoint FIFO

Configuration

The Hi-Speed USB module has a set of common registers and a set of indexed registers for configuration of the individual endpoints. The indexed endpoint configuration registers are accessed for a specific endpoint by selecting that endpoint using in the INDEX register. For additional information on the configuration and operation of the Hi-Speed USB module, please refer to the documentation, firmware and application examples provided by Microchip and third-party solution providers for PIC32 products. For information about fully USB IF compliant middleware, please refer to available third-party solutions.

Note: At startup, it is necessary to load the calibration values from CALTOP.FCCFG67 into the PHY00 register. See the Memories section for details about CALTOP.FCCFG67.

Operating Speed

The Hi-Speed USB module supports operation in Hi-Speed (480 Mb/s), Full Speed (12 Mb/s) and Low Speed (1.5 Mb/s).

  • Hi-Speed operation can be enabled or disabled using the HSEN bit in the POWR register.
  • Operation in Full-Speed and Hi-Speed modes can be forced in the TESTMODE register for testing purposes.
  • The operating speed is set using the SPEED bits of the configuration registers for the individual endpoints.