37.7 Register Summary: USB Common Registers

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	31:24
		23:16
		15:8						REFCLKSEL	IDOVEN	IDVAL
		7:0							ENABLE	SWRST
0x04	CTRLB	31:24
		23:16					BLANK[19:16]
		15:8	BLANK[15:8]
		7:0	BLANK[7:0]
0x08	CTRLC	31:24
		23:16
		15:8
		7:0				T1MSEN
0x0C	INTENCLR	31:24
		23:16
		15:8
		7:0			PHYRDY	T1MS	DMA	USB	RESUME	WAKEUP
0x10	INTENSET	31:24
		23:16
		15:8
		7:0			PHYRDY	T1MS	DMA	USB	RESUME	WAKEUP
0x14	INTFLAG	31:24
		23:16
		15:8
		7:0			PHYRDY	T1MS	DMA	USB	RESUME	WAKEUP
0x18	STATUS	31:24
		23:16
		15:8
		7:0						VREGRDY	PHYON	PHYRDY
0x1C	SYNCBUSY	31:24
		23:16
		15:8
		7:0						T1MSEN	ENABLE	SWRST
0x20 ... 0x1000	Reserved
0x1001	POWR	7:0	ISOUPD	SOFTCONN	HSEN	HSMODE	RESET	RESUME	SUSPMODE	SUSPEN
0x1002	INTRTX	15:8
0x1002	INTRTX	7:0	EP6TXIF	EP5TXIF	EP4TXIF	EP3TXIF	EP2TXIF	EP1TXIF	EP0TXIF	EP0IF
0x1004	INTRRX	15:8
0x1004	INTRRX	7:0	EP6RXIF	EP5RXIF	EP4RXIF	EP3RXIF	EP2RXIF	EP1RXIF	EP0RXIF
0x1006	INTRTXE	15:8
0x1006	INTRTXE	7:0	EP6TXEN	EP5TXEN	EP4TXEN	EP3TXEN	EP2TXEN	EP1TXEN	EP0TXEN	EP0EN
0x1008	INTRRXE	15:8
0x1008	INTRRXE	7:0	EP6RXEN	EP5RXEN	EP4RXEN	EP3RXEN	EP2RXEN	EP1RXEN	EP0RXEN
0x100A	INTRUSB	7:0	VBUSERR	SESSREQ	DISCON	CONN	SOF	RESET	RESUME	SUSPEND
0x100B	INTRUSBE	7:0	VBUSERREN	SESSREQEN	DISCONEN	CONNEN	SOFEN	RESETEN	RESUMEEN	SUSPENDEN
0x100C	FRAME	15:8						FRMNUM[10:8]
0x100C	FRAME	7:0	FRMNUM[7:0]
0x100E	INDEX	7:0					SELEP[3:0]
0x100F	TESTMODE	7:0	FORCEHOST	FIFOACCESS	FORCEFS	FORCEHS	TESTPACKET	TESTK	TESTJ	TESTSE0NAK
0x1010	TXMAXP	15:8	MULT[4:0]					TXMAXP[10:8]
0x1010	TXMAXP	7:0	TXMAXP[7:0]
0x1012 ... 0x1013	Reserved
0x1014	RXMAXP	15:8	MULT[4:0]					RXMAXP[10:8]
0x1014	RXMAXP	7:0	RXMAXP[7:0]
0x1016 ... 0x101E	Reserved
0x101F	FIFOSIZE	7:0	RXFIFOSIZE[3:0]				TXFIFOSIZE[3:0]
0x1020	FIFO0	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x1024	FIFO1	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x1028	FIFO2	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x102C	FIFO3	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x1030	FIFO4	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x1034	FIFO5	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x1038	FIFO6	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x103C	FIFO7	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0x1040 ... 0x105F	Reserved
0x1060	DEVCTL	7:0	BDEVICE	FSDEV	LSDEV	VBUS[1:0]		HOSTMODE	HOSTREQ	SESSION
0x1061	MISC	7:0							TXEDMA	RXEDMA
0x1062	TXFIFOSZ	7:0				DPB	FIFOSZ[3:0]
0x1063	RXFIFOSZ	7:0				DPB	FIFOSZ[3:0]
0x1064	TXFIFOADD	15:8				ADDR[12:8]
0x1064	TXFIFOADD	7:0	ADDR[7:0]
0x1066	RXFIFOADD	15:8				ADDR[12:8]
0x1066	RXFIFOADD	7:0	ADDR[7:0]
0x1068 ... 0x1077	Reserved
0x1078	EPIINFO	7:0	RXENDPOINTS[3:0]				TXENDPOINTS[3:0]
0x1079	Reserved
0x107A	LINKINFO	7:0	WTCON[3:0]				WTID[3:0]
0x107B	VPLEN	7:0	VPLEN[7:0]
0x107C	HSEOF1	7:0	HSEOF1[7:0]
0x107D	FSEOF1	7:0	FSEOF1[7:0]
0x107E	LSEOF1	7:0	LSEOF1[7:0]
0x107F	SOFTRST	7:0							NRSTX	NRST
0x1080 ... 0x11FF	Reserved
0x1200	DMAINTR	31:24
		23:16
		15:8
		7:0	DMA7IF	DMA6IF	DMA5IF	DMA4IF	DMA3IF	DMA2IF	DMA1IF	DMA0IF
0x1204	DMA0CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x1208	DMA0ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x120C	DMA0NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x120E	DMA1CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x1212	DMA1ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x1216	DMA1NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x1218	DMA2CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x121C	DMA2ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x1220	DMA2NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x1222	DMA3CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x1226	DMA3ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x122A	DMA3NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x122C	DMA4CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x1230	DMA4ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x1234	DMA4NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x1236	DMA5CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x123A	DMA5ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x123E	DMA5NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x1240	DMA6CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x1244	DMA6ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x1248	DMA6NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x124A	DMA7CTRL	31:24
		23:16
		15:8						DMABRSTM[1:0]		DMAERR
		7:0	DMAEP[3:0]				DMAIE	DMAMODE	DMADIR	DMAEN
0x124E	DMA7ADDR	31:24	DMAADDR[31:24]
		23:16	DMAADDR[23:16]
		15:8	DMAADDR[15:8]
		7:0	DMAADDR[7:0]
0x1252	DMA7NCOUNT	31:24	DMACOUNT[31:24]
		23:16	DMACOUNT[23:16]
		15:8	DMACOUNT[15:8]
		7:0	DMACOUNT[7:0]
0x1256 ... 0x133F	Reserved
0x1340	RXDPKTBUFDIS	15:8
0x1340	RXDPKTBUFDIS	7:0	EP6RXD	EP5RXD	EP4RXD	EP3RXD	EP2RXD	EP1RXD	EP0RXD
0x1342	TXDPKTBUFDIS	15:8
0x1342	TXDPKTBUFDIS	7:0	EP6TXD	EP5TXD	EP4TXD	EP3TXD	EP2TXD	EP1TXD	EP0TXD
0x1344	CTUCH	15:8	TUCH[15:8]
0x1344	CTUCH	7:0	TUCH[7:0]
0x1346	CTHHSRTN	15:8	THHSRTN[15:8]
0x1346	CTHHSRTN	7:0	THHSRTN[7:0]
0x1348	CTHSBT	15:8
0x1348	CTHSBT	7:0					HSTMEOUTADD[3:0]
0x134A ... 0x135F	Reserved
0x1360	LPMATTR	15:8	ENDPOINT[3:0]							RMTWAK
0x1360	LPMATTR	7:0	HIRD[3:0]				LNKSTATE[3:0]
0x1362	LPMCNTRL	7:0				LPMNAK	LPMEN[1:0]		LPMRES	LPMXMT
0x1363	LPMINTREN	7:0			LPMERREN	LPMRESEN	LPMNCEN	LPMACKEN	LPMNYEN	LPMSTEN
0x1364	LPMINTR	7:0			LPMERR	LPMRES	LPMNC	LPMACK	LPMNY	LPMST

PIC32CZ CA80/CA90 Family

37.7 Register Summary: USB Common Registers