24.9.1 Control A in Clock/Calendar mode (CTRLA.MODE=2)

Important: When the RTC is disabled (writing CTRLA.ENABLE = 0), the SYNCBUSY.ENABLE will be set to ‘0’ before the TAMPER detection is disabled. Changing the tamper configuration (TAMCTRL, TAMPCTRLB, CTRLB, EVCTRL) during that time can produce a false tamper detection. After the fall of SYNCBUSY.ENABLE, the firmware must wait for at least 1 RTC clock period before changing the tamper configuration.
Table 24-37. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 15141312111098 
 CLOCKSYNCGPTRST  PRESCALER[3:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
 MATCHCLRCLKREP  MODE[1:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable

The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the CLOCK register.

This bit is not enable-protected.

ValueDescription
0CLOCK read synchronization is disabled
1CLOCK read synchronization is enabled

Bit 14 – GPTRST GP Registers Reset On Tamper Enable

Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled.

This bit is no synchronized.

Bits 11:8 – PRESCALER[3:0] Prescaler

These bits define the prescaler factor for the RTC clock source (CLKSELCTRL.RTCSEL -> CLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized.

CLK_RTC_CNT = [CLK_RTC / 2(PRESCALAR-1)]

ValueNameDescription
0x0OFFCLK_RTC_CNT = GCLK_RTC/1
0x1DIV1CLK_RTC_CNT = GCLK_RTC/1
0x2DIV2CLK_RTC_CNT = GCLK_RTC/2
0x3DIV4CLK_RTC_CNT = GCLK_RTC/4
0x4DIV8CLK_RTC_CNT = GCLK_RTC/8
0x5DIV16CLK_RTC_CNT = GCLK_RTC/16
0x6DIV32CLK_RTC_CNT = GCLK_RTC/32
0x7DIV64CLK_RTC_CNT = GCLK_RTC/64
0x8DIV128CLK_RTC_CNT = GCLK_RTC/128
0x9DIV256CLK_RTC_CNT = GCLK_RTC/256
0xADIV512CLK_RTC_CNT = GCLK_RTC/512
0xBDIV1024CLK_RTC_CNT = GCLK_RTC/1024
0xC-0xF-Reserved

Bit 7 – MATCHCLR Clear on Match

This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized.
ValueDescription
0The counter is not cleared on a Compare/Alarm 0 match
1The counter is cleared on a Compare/Alarm 0 match

Bit 6 – CLKREP Clock Representation

This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized.
ValueDescription
024 Hour
112 Hour (AM/PM)

Bits 3:2 – MODE[1:0] Operating Mode

This field defines the operating mode of the RTC. This bit is not synchronized.
ValueNameDescription
0x0COUNT32Mode 0: 32-bit counter
0x1COUNT16Mode 1: 16-bit counter
0x2CLOCKMode 2: Clock/calendar
0x3-Reserved

Bit 1 – ENABLE Enable

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0The peripheral is disabled
1The peripheral is enabled

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete.

This bit is not enable-protected.

ValueDescription
0There is not reset operation ongoing
1The reset operation is ongoing