38.6.2.1 Software Initialization

Software initialization is started by setting CCCR.INIT bit (CCCR <0>), either by software, or by going “bus off.” While CCCR.INIT bit (CCCR <0>) is set, message transfer from and to the CAN bus is stopped, the status of the CAN bus output CANx_TX is ”recessive” (HIGH). The counters of the Error Management Logic EML are unchanged. Setting CCCR.INIT bit (CCCR <0>) does not change any configuration register. Resetting CCCR.INIT bit (CCCR <0>) finishes the software initialization. Afterwards the Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive ”recessive” bits (= Bus_Idle) before it can take part in bus activities and start the message transfer.

Access to the CAN configuration registers is only enabled when both bits, CCCR.CCE bit (CCCR <1>) and CCCR.INIT bit (CCCR <0>) are set (protected write).

CCCR.CCE bit (CCCR <1>) can only be set and cleared while CCCR.INIT bit (CCCR <0>) = ‘1’. CCCR.CCE bit (CCCR <1>) is automatically cleared when CCCR.INIT bit (CCCR <0>) is cleared.

The following registers are reset when CCCR.CCE bit (CCCR <1>) is set

  • HPMS - High Priority Message Status
  • RXF0S - Rx FIFO 0 Status
  • RXF1S - Rx FIFO 1 Status
  • TXFQS - Tx FIFO/Queue Status
  • TXBRP - Tx Buffer Request Pending
  • TXBTO - Tx Buffer Transmission Occurred
  • TXBCF - Tx Buffer Cancellation Finished
  • TXEFS - Tx Event FIFO Status

The Timeout Counter value TOCV.TOC bits (TOCV <15:0>) is preset to the value configured by TOCC.TOP bits (TOCC <31:16>) when CCCR.CCE bit (CCCR <1>) is set.

In addition the state machines of the Tx Handler and Rx Handler are held in idle state while CCCR.CCE bit (CCCR <1>) = ‘1’.

The following registers are only writable while CCCR.CCE bit (CCCR <1>) = ‘0’

  • TXBAR - Tx Buffer Add Request
  • TXBCR - Tx Buffer Cancellation Request

CCCR.TEST bit (CCCR <7>) and CCCR.MON bit (CCCR <5>) can only be set by the CPU while CCCR.INIT bit (CCCR <0>) = ‘1’ and CCR.CCE bit (CCCR <1>) = ‘1’. Both bits may be cleared at any time. CCCR.DAR bit (CCCR <6>) can only be set/cleared while CCCR.INIT bit (CCCR <0>) = ‘1’ and CCCR.CCE bit (CCCR <1>) = ‘1’.