35.4 Peripheral Dependencies


Peripheral Name	Base Address	NVIC IRQ Index:Source	MCLK AXI/APB Clocks Index:Name ⁽¹⁾	GCLK Peripheral Channel Index:Clock Name ⁽²⁾	PAC Peripheral Peripheral Identifier (PAC.WRCTRL)	DMA Trigger Index:Source (DMAC.CHCTRLBk)	Power Domain
SERCOM0	0x4600 0000 (APB E)	55 : ERROR; 56 : RXBRK 57 : DRE/PREC; 58 : TXC/AMATCH 59 : RXC/DRDY; 60 : RXS/SSL/TXFE 61 : CTSIC/RXFF	MCLK.CLKMSK0[31]	18 : GCLK_SERCOM0_SLOW 21 : GCLK_SERCOM0_CORE	23	5 : RX 6 : TX	VDDREG
SERCOM1	0x4600 2000 (APB E)	62 : ERROR; 63 : RXBRK 64 : DRE/PREC; 65 : TXC/AMATCH 66 : RXC/DRDY; 67 : RXS/SSL/TXFE 68 : CTSIC/RXFF	MCLK.CLKMSK1[0]	18 : GCLK_SERCOM1_SLOW 22 : GCLK_SERCOM1_CORE	24	7 : RX 8 : TX	VDDREG
SERCOM2	0x4580 0000 (APB D)	69 : ERROR; 70 : RXBRK 71 : DRE/PREC; 72 : TXC/AMATCH 73 : RXC/DRDY; 74 : RXS/SSL/TXFE 75 : CTSIC/RXFF	MCLK.CLKMSK1[1]	19 : GCLK_SERCOM2_SLOW 23 : GCLK_SERCOM2_CORE	25	9 : RX 10 : TX	VDDREG
SERCOM3	0x4580 2000 (APB D)	76 : ERROR; 77 : RXBRK 78 : DRE/PREC; 79 : TXC/AMATCH 80 : RXC/DRDY; 81 : RXS/SSL/TXFE 82 : CTSIC/RXFF	MCLK.CLKMSK1[2]	19 : GCLK_SERCOM3_SLOW 24 : GCLK_SERCOM3_CORE	26	11 : RX 12 : TX	VDDREG
SERCOM4	0x4600 4000 (APB E)	83 : ERROR; 84 : RXBRK 85 : DRE/PREC; 86 : TXC/AMATCH 87 : RXC/DRDY; 88 : RXS/SSL/TXFE 89 : CTSIC/RXFF	MCLK.CLKMSK1[3]	18 : GCLK_SERCOM4_SLOW 25 : GCLK_SERCOM4_CORE	27	13 : RX 14 : TX	VDDREG
SERCOM5	0x4580 4000 (APB D)	90 : ERROR; 91 : RXBRK 92 : DRE/PREC; 93 : TXC/AMATCH 94 : RXC/DRDY; 95 : RXS/SSL/TXFE 96 : CTSIC/RXFF	MCLK.CLKMSK1[4]	19 : GCLK_SERCOM5_SLOW 26 : GCLK_SERCOM5_CORE	28	15 : RX 16 : TX	VDDREG
SERCOM6	0x4580 6000 (APB D)	97 : ERROR; 98 : RXBRK 99 : DRE/PREC; 100 : TXC/AMATCH 101 : RXC/DRDY; 102 : RXS/SSL/TXFE 103 : CTSIC/RXFF	MCLK.CLKMSK1[5]	19 : GCLK_SERCOM6_SLOW 27 : GCLK_SERCOM6_CORE	29	17 : RX 18 : TX	VDDREG
SERCOM7	0x4500 0000 (APB B)	104 : ERROR; 105 : RXBRK 106 : DRE/PREC; 107 : TXC/AMATCH 108 : RXC/DRDY; 109 : RXS/SSL/TXFE 110 : CTSIC/RXFF	MCLK.CLKMSK1[6]	20 : GCLK_SERCOM7_SLOW 28 : GCLK_SERCOM7_CORE	30	19 : RX 20 : TX	VDDREG
SERCOM8	0x4500 2000 (APB B)	111 : ERROR; 112 : RXBRK 113 : DRE/PREC; 114 : TXC/AMATCH 115 : RXC/DRDY; 116 : RXS/SSL/TXFE 117 : CTSIC/RXFF	MCLK.CLKMSK1[7]	20 : GCLK_SERCOM8_SLOW 29 : GCLK_SERCOM8_CORE	31	21 : RX 22 : TX	VDDREG
SERCOM9	0x4500 4000 (APB B)	118 : ERROR; 119 : RXBRK 120 : DRE/PREC; 121 : TXC/AMATCH 122 : RXC/DRDY; 123 : RXS/SSL/TXFE 124 : CTSIC/RXFF	MCLK.CLKMSK1[8]	20 : GCLK_SERCOM9_SLOW 30 : GCLK_SERCOM9_CORE	32	23 : RX 24 : TX	VDDREG
Note: Register Field: MCLK.CLKMSK{index/32}.MASK[index mod 32]. See GCLK.PCHCTRLm register, where m = Index. The GCLK_SERCOMn_SLOW setting must only be used for the I²C operating mode.

I/O Lines

Using the SERCOM I/O lines requires the I/O pins to be configured using port configuration (PORT). The SERCOM has four internal pads, PAD[3:0], and the signals from I²C, SPI and USART are routed through these SERCOM pads through a multiplexer. The configuration of the multiplexer is available from the different SERCOM modes. Refer to the mode specific sections below for additional information.

Power Management

The SERCOM can operate in any Sleep mode provided the selected clock source is running. SERCOM interrupts can be configured to wake the device from sleep modes.

Clocks

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. The SERCOM APB BUS interface clocks are enabled by default on reset.

The SERCOM uses two generic clocks: GCLK_SERCOMx_CORE and GCLK_SERCOMx_SLOW. The core clock (GCLK_SERCOMx_CORE) is required to clock the SERCOM while working as a host. The slow clock (GCLK_SERCOMx_SLOW) is only required for certain functions. See specific mode sections below for details.

These clocks must be configured and enabled in the Generic Clock Controller (GCLK) before using the SERCOM.

The generic clocks are asynchronous to the user interface clock (CLK_SERCOMx_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to Synchronization for details.

DMA

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before the SERCOM DMA requests are used.

Concurrent DMA and CPU accesses to the DATA register must be avoided, as this may lead to unpredictable behavior.

Debug Operation

When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during debugging. This peripheral can be forced to halt operation during debugging. Refer to the Debug Control (DBGCTRL) register for details.

Register Access Protection

All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:

Interrupt Flag Clear and Status register (INTFLAG)
Status register (STATUS)
Data register (DATA)
Address register (ADDR)

Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description.

PAC write protection does not apply to accesses through an external debugger.

PIC32CZ CA80/CA90 Family