35.8.5.4 DMA and Interrupts
This chapter provides DMA and interrupt conditions when the FIFO is disabled. For details when the FIFO is enabled, refer to FIFO Support.
Each interrupt source has its own Interrupt flag. The Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) will be set when the Interrupt condition is met. Each interrupt can be individually enabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing ‘1’ to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the Interrupt flag is set and the corresponding interrupt is enabled. The interrupt request is active until the Interrupt flag is cleared, the interrupt is disabled or the I2C is reset. See the INTFLAG (Client) or INTFLAG (Host) register for details on how to clear Interrupt flags.
| Condition | Request DMA | Interrupt | Event |
|---|---|---|---|
| Data needed for transmit
(TX) (Client Transmit mode) | Yes (request cleared when data is written) | N/A | |
| Data received (RX) (Client Receive mode) | Yes (request cleared when data is read) | ||
| Data Ready (DRDY) | Yes | ||
| Address Match (AMATCH) | Yes | ||
| Stop received (PREC) | Yes | ||
| TX FIFO Empty (TXFE) | Yes | ||
| RX FIFO Full (RXFF) | Yes | ||
| Error (ERROR) | Yes |
| Condition | Request DMA | Interrupt | Event |
|---|---|---|---|
| Data needed for transmit
(TX) (Host Transmit mode) | Yes (request cleared when data is written) | N/A | |
| Data needed for transmit
(RX) (Host Transmit mode) | Yes (request cleared when data is read) | ||
| Host on Bus (MB) | Yes | ||
| Stop received (SB) | Yes | ||
| TX FIFO Empty (TXFE) | Yes | ||
| RX FIFO Full (RXFF) | Yes | ||
| Error (ERROR) | Yes |