14.7.15 Voltage Regulator System (VREG) Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | VREG |
| Offset: | 0x3C |
| Reset: | 0x0X02 |
| Property: | Write-Protected |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FORCELDO | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 1 |
Bit 13 – FORCELDO Force LDO Voltage Regulator
| Value | Description |
|---|---|
| 0 | The voltage regulator is in low-power and low-drive configuration in Standby Sleep mode |
| 1 | The voltage regulator is in low-power and high-drive configuration in Standby Sleep mode |
Bit 6 – RUNSTDBY Run in Standby
| Value | Description |
|---|---|
| 0 | The voltage regulator is in low-power configuration in Standby Sleep mode |
| 1 | The voltage regulator is in normal configuration in Standby Sleep mode |
Bit 1 – ENABLE
Must be set to 1.