13.6.14 Reset Cause
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RCAUSE |
| Offset: | 0x38 |
| Reset: | 0x01 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYST | WDT | EXT | BOD33 | BOD12 | POR | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 |
Bit 6 – SYST System Reset Request
This bit is set if a system Reset request has been performed. Refer to the Cortex processor documentation for more details.
Bit 5 – WDT Watchdog Reset
This flag is set if a Watchdog Timer Reset occurs.
Bit 4 – EXT External Reset
This flag is set if an external Reset occurs.
Bit 2 – BOD33 Brown-Out 33 Detector Reset
This flag is set if a BOD33 Reset occurs.
Bit 1 – BOD12 Brown-Out 12 Detector Reset
This flag is set if a BOD12 Reset occurs.
Bit 0 – POR Power-On Reset
This flag is set if a POR occurs.