13.6.2 Sleep Mode
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SLEEP |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IDLE[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bits 1:0 – IDLE[1:0] Idle Mode Configuration
These bits select the Idle mode configuration after a WFI
instruction.
| IDLE[1:0] | Name | Description |
|---|---|---|
| 0x0 | CPU | The CPU clock domain is stopped |
| 0x1 | AHB | The CPU and AHB clock domains are stopped |
| 0x2 | APB | The CPU, AHB and APB clock domains are stopped |
| 0x3 | Reserved |