13.6.9 APBB Mask
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | APBBMASK |
| Offset: | 0x1C |
| Reset: | 0x0000007F |
| Property: | Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PORT | NVMCTRL | DSU | PAC1 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 1 | 1 | 1 |
Bit 3 – PORT PORT APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the PORT is stopped. |
| 1 | The APBB clock for the PORT is enabled. |
Bit 2 – NVMCTRL NVMCTRL APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the NVMCTRL is stopped. |
| 1 | The APBB clock for the NVMCTRL is enabled. |
Bit 1 – DSU DSU APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the DSU is stopped. |
| 1 | The APBB clock for the DSU is enabled. |
Bit 0 – PAC1 PAC1 APB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the PAC1 is stopped. |
| 1 | The APBB clock for the PAC1 is enabled. |