5.1 PRBS Generator/Checker

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Each transceiver has embedded blocks with a built-in PRBS generator and checker that can be used to perform link testing and diagnostics. These test capabilities are available to the user through the SmartDebug toolset. For more information on PRBS generator and checker, see SmartBERT.

The implementation of the PRBS generator uses a linear feedback shift register (LFSR). The generator produces a pre-defined sequence of 1s and 0s, occurring with the same probability. A sequence of consecutive n × (2^{n -1}) bits comprise one data pattern, and this pattern repeats itself over time. This sequence is compared within the checker to ensure no errors in the sequence are detected.

The PRBS generator/checker supports the following test patterns for 32- and 40-bit wide PMA parallel buses.

PRBS31: x³¹ + x²⁸ + 1
PRBS23: x²³ + x¹⁸ + 1
PRBS15: x¹⁵ + x¹⁴ + 1
PRBS9: x⁹ + x⁵ +1
PRBS7: x⁷ + x⁶ + 1

PRBS7 is also supported in widths of 8, 10, 16, and 20 bits.

Note: Some PRBS pattern polynomials are used as part of several standards such as ITU-T recommendations. The PRBS7 polynomial is not necessarily a telecommunications standard but is typically used by test equipment because its similarity with 8b10b-encoded patterns.

The PRBS checker is on the parallel side of the de-serializer. If LANE#_RX_SLIP is toggled during PRBS testing, then the next word will not be in the same PRBS pattern as the one before it which causes a failure to match.