5.3 Dynamic Reconfiguration Interface

The dynamic reconfiguration interface (DRI) is used with transceiver to access the memory map of the transceiver blocks. DRI is an APB slave that allows global access to all transceiver lanes, PCIe blocks, transmit PLLs, and FPGA PLLs. The DRI allows changing key features of the transceiver before and during operation. The DRI connectivity is dedicated within the device requiring no FPGA fabric routing. For more information about DRI, see PolarFire Family Device Power-Up and Resets User Guide and PolarFire Family DRI User Guide. For information about design targeted configuration, see Transceiver Initialization Data.

Care must be exercised when using the DRI to alter transceiver settings as changes from the factory settings can cause undesired results.

Figure 5-2. PF_DRI Example
Note: For implementation example, see AN4592: PolarFire FPGA Dynamic Reconfiguration Interface Application Note (Earlier AC475).
Note:

** The PCIESS blocks do not connect directly to a DRI port, however, the associated XCVR LANE for Quad0 must be connected to the DRI for dynamic control of the XCVR features used with PCIESS. The PCIE[0:1] blocks have dedicated APB port for access to the register control within the PCIE subsystem.