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PolarFire Family Transceiver User Guide
PolarFire Family Transceiver User Guide
  1. Home
  2. 5 Debug and Testing
  3. 5.2 Loopback
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  • Introduction
  • 1 Functional Description
  • 2 Implementation
  • 3 Signal Integrity Conditioning
  • 4 Simulation
  • 5 Debug and Testing
    • 5.1 PRBS Generator/Checker
    • 5.2 Loopback
      • 5.2.1 EQ Far-End Loopback
      • 5.2.2 EQ Near-End Loopback
      • 5.2.3 CDR Far-End Loopback
    • 5.3 Dynamic Reconfiguration Interface
  • 6 Board Design Recommendations
  • 7 Revision History
  • Microchip FPGA Support
  • Microchip Information

5.2 Loopback

(Ask a Question)

There are three loopbacks supported within the transceiver blocks to assist designers in debugging the system by segmenting the link (Figure   1). The loopbacks are accessed through the SmartDebug tools. For information about data rate performance of loopback paths, see respective PolarFire FPGA Datasheet or PolarFire SoC Datasheet .

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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