6.1 Transceiver Top-Level Pin Out

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The transceiver quad includes four differential receive and transmit pairs. The reference clock to the transmit PLLs can be provided either by the provided primary differential reference clock pins or by the FPGA clock resources.

The transceiver pins, power pins, and associated clock are listed in the following table.

Table 6-1. Transceiver Device Level Pin List (continued)¹
Pin Name^²	Direction	Description
XCVR_#_TX3_P	Output	Transmit data. Transceiver differential positive output. Each transceiver quad consists of four transmit+ signals.
XCVR_#_TX2_P	Output	Transmit data. Transceiver differential positive output. Each transceiver quad consists of four transmit+ signals.
XCVR_#_TX1_P	Output	Transmit data. Transceiver differential positive output. Each transceiver quad consists of four transmit+ signals.
XCVR_#_TX0_P	Output	Transmit data. Transceiver differential positive output. Each transceiver quad consists of four transmit+ signals.
XCVR_#_TX3_N	Output	Transmit data. Transceiver differential negative output. Each transceiver quad consists of four transmit− signals.
XCVR_#_TX2_N	Output	Transmit data. Transceiver differential negative output. Each transceiver quad consists of four transmit− signals.
XCVR_#_TX1_N	Output	Transmit data. Transceiver differential negative output. Each transceiver quad consists of four transmit− signals.
XCVR_#_TX0_N	Output	Transmit data. Transceiver differential negative output. Each transceiver quad consists of four transmit− signals.
XCVR_#_RX3_P	Input	Receive data. Transceiver differential positive input. Each transceiver quad consists of four receive+ signals.
XCVR_#_RX2_P	Input	Receive data. Transceiver differential positive input. Each transceiver quad consists of four receive+ signals.
XCVR_#_RX1_P	Input	Receive data. Transceiver differential positive input. Each transceiver quad consists of four receive+ signals.
XCVR_#_RX0_P	Input	Receive data. Transceiver differential positive input. Each transceiver quad consists of four receive+ signals.
XCVR_#_RX3_N	Input	Receive data. Transceiver differential negative input. Each transceiver quad consists of four receive− signals.
XCVR_#_RX2_N	Input	Receive data. Transceiver differential negative input. Each transceiver quad consists of four receive– signals.
XCVR_#_RX1_N	Input	Receive data. Transceiver differential negative input. Each transceiver quad consists of four receive– signals.
XCVR_#_RX0_N	Input	Receive data. Transceiver differential negative input. Each transceiver quad consists of four receive– signals.
XCVR_#[A,B,C]_REFCLK_P^³	Input	This pin is used as the positive terminal when used with a differential clock source.
XCVR_#[A,B,C]_REFCLK_N³	Input	This pin is used as the negative terminal when used with a differential clock.
XCVR_VREF	Power	This pin is used as a reference voltage for the REFCLK input buffers. It is used for single-ended clock signals. This signal is common for all transceiver on device.
VDDA25	Power	2.5 V analog supply. All transmit PLLs and associated high-speed clock routes in each transceiver PMA are connected on-chip but isolated from the other transmit PLLs on the device.
VDDA	Power	Supply for receive, transmit, and common circuits. Common for all lanes within the PMA block.
VDD_XCVR_CLK	Power	Provides common power to all transceiver reference clock buffers. VDD_XCVR_CLK power supply operates using a voltage of  2.5 V to 3.3 V.
⁽¹⁾ See the related PolarFire Package Pin Assignment Table or PolarFire SoC Package Pin Assignment Table for recommended USED or UNUSED conditions. ⁽²⁾ # Indicates the associated transceiver quad (that is, Q0=0, Q1=1, …Q5=5). ⁽³⁾ There is one pin per transmit PLL per transceiver quad. There is a minimum of two differential reference clock input pairs per quad with an additional pair for specific quads. It is limited to driving only one clock source for the transceiver block when used differentially or two when used in the single-ended mode.