3.2 DC/AC Characteristics


T_A = T_J = +25°C; VIN = SVIN = PVINx = LVIN = 5V; L1 = L2 = L3 = L4 = 1.5 µH; COUT1 = COUT2 = COUT3 = COUT4 = 22 µF, unless otherwise specified. Bold values indicate –40°C ≤ T_J ≤ +125°C.
Parameters	Symbol	Min.	Typ.	Max.	Units	Conditions
System Input Supply
Supply Voltage Range	V_IN	2.7	—	5.5	V	—
Undervoltage Lockout Threshold	V_{UVLO_TH}	2.4	2.55	2.7	V	EN and PWRHLD tied to VIN
Undervoltage Lockout Hysteresis	V_{UVLO_HYS}	—	125	—	mV	—
Shutdown (OFF) Current	I_SHDN	—	—	13	µA	EN = PWRHLD = LPM = HPM = 0, nRSTO, nSTRTO, nINTO floating, VIN = 5.5V
Shutdown (OFF) Current	I_{SHDN_105}	—	—	10	µA	EN = PWRHLD = LPM = HPM = 0, nRSTO, nINTO floating, VIN = 4.5V, T_J = −40 to 105°C (Note 1)
HIBERNATE Mode Operational Quiescent Current (switching, buck2 ON, Note 2)	I_{QOP_HIB2}	—	165	—	µA	I_OUT2 = 0mA, buck2 ON (V_OUT2 = 1.2V), all other channels OFF, EN = LPM = 1, PWRHLD = HPM = 0
Low-Power Mode Operational Quiescent Current (switching, Note 2)	I_{QOP_LPM}	—	290	—	µA	IOUTx = 0mA, all channels ON, EN = PWRHLD = LPM = 1, HPM = 0
Active Mode Operational Quiescent Current (switching, Note 2)	I_{QOP_ACT}	—	16	—	mA	IOUTx = 0mA, all channels enabled, EN = PWRHLD = 1, LPM = HPM = 0
High-Performance Active Mode Operational Quiescent Current (switching, Note 2)	I_{QOP_HPM}	—	16	—	mA	IOUTx = 0mA, all channels enabled, EN = PWRHLD = HPM = 1, LPM = 0
Timebase
Timebase Accuracy	ACC_TB	−10	—	+10	%	FSD[1:0] = 00, 01
Thermal Protection and Warning
Overtemperature Shutdown Threshold (Note 2)	T_TSD	—	160	—	°C	Bit TSD to 1
Overtemperature Shutdown Hysteresis (Note 2)	T_{TSD_HYS}	—	20	—	°C	Bit TSD to 0
Overtemperature Warning Threshold (Note 2)	T_TWR	—	135	—	°C	Bit TWR to1
Overtemperature Warning Hysteresis (Note 2)	T_{TWR_HYS}	—	10	—	°C	Bit TWR to 0
Notes: Maximum limit for T_J= −40°C to +125°C based on characterization data. Not production tested.


T_A = +25°C; VIN = SVIN = PVINx = LVIN = 5V; V_OUT1 = 3.3V, L1 = 1.5 µH; C_OUT1 = 22 µF, unless otherwise specified. Bold values indicate –40°C ≤ T_J ≤ +125°C.
Parameters	Symbol	Min.	Typ.	Max.	Units	Conditions
Buck1
Input Operating Voltage Range	V_PVIN1	2.7	—	5.5	V	—
Output Voltage Range	V_OUT1	1.2	—	3.7	V	—
Output Voltage Step	V_step	—	50	—	mV	—
PVIN1 Shutdown Current	I_{PVIN1_SHDN}	—	0.05	2	µA	Regulator disabled, PVIN1 = 5V
Operational Quiescent Current, AutoPFM, default setting (Note 1)	I_{QOP_PFM1}	—	45	—	µA	I_OUT1 = 0mA, Auto PFM EN = PWRHLD = LPM = 1, HPM = 0 B1HCEN = 0 (default) ΔI_Q for buck1 activated
Operational Quiescent Current, AutoPFM + HCM (Note 1)	I_{QOP_HCM}	—	47	—	µA	I_OUT1 = 0mA, Auto PFM PWRHLD = LPM = 1, HPM = 0, B1HCEN = 1 ΔI_Q for buck1 activated
Output Voltage Accuracy, FPWM	ACC_OUT_PWM1	−2	—	+2	%	I_OUT1 = 0mA
Output Voltage Accuracy, Auto-PFM	ACC_OUT_PFM1	−2	—	+2	%	I_OUT1 = 0mA B1HCEN = 0
Output Voltage Line Regulation (Note 1)	LINE_REG_PWM1	—	0.03	—	%	I_OUT1 = 0mA, FPWM, V_IN = PVIN1 = SVIN = 3.6V to 5.5V
Output Voltage Line Regulation (Note 1)	LINE_REG_PFM1	—	0.07	—	%	I_OUT1 = 0mA, Auto PFM, V_IN = PVIN1 = SVIN = 3.6V to 5.5V
Output Voltage Load Regulation (Note 1)	LOAD_REG_PWM1	—	0.3	—	%	I_OUT1 = 0A to 1A, FPWM
Output Voltage Load Regulation (Note 1)	LOAD_REG_PFM1	—	0.5	—	%	I_OUT1 = 0A to 1A, Auto PFM
Hysteretic Control Mode Upper Regulation Threshold, Auto-PFM	HCM_TH	1.7	2.9	4.3	%	I_OUT1 = 0mA EN = PWRHLD = LPM = 1, HPM = 0 B1HCEN = 1 SVIN = PVIN1 = 1.06 V_{OUT1_NOM} OUT1 rising, % of V_{OUT1_NOM}
Hysteretic Control Mode Disable Threshold, Auto-PFM	HCM_DIS	—	11.1	—	%	I_OUT1 = 0mA EN = PWRHLD = LPM = 1, HPM = 0 B1HCEN = 1 SVIN = PVIN1 rising, % of V_{OUT1_NOM}
Hysteretic Control Mode Enable Threshold, Auto-PFM	HCM_EN	5	9	13	%	I_OUT1 = 0mA EN = PWRHLD = LPM = 1, HPM = 0 B1HCEN = 1 SVIN = PVIN1 falling, % of V_{OUT1_NOM}
Switching Frequency	f_sw	1.8	2	2.2	MHz	FPWM, FSD[1:0] = 00,01
Switching Frequency Displacement	FSD_10	—	−16.5	—	%	FPWM, FSD[1:0] = 10
Switching Frequency Displacement	FSD_11	—	+16.5	—	%	FPWM, FSD[1:0] = 11
Maximum Duty Cycle	D_MAX	100	—	—	%	Functionality test
Minimum ON Time	T_{ON_MIN1}	—	35	—	ns	FPWM
High-Side Switch ON-Resistance	R_DsonP1	—	140	160	mΩ	PVIN1 = SVIN = 5V
Low-Side Switch ON-Resistance	R_DsonN1	—	120	140	mΩ	PVIN1 = SVIN = 5V
POK (Power OK) Threshold	POK_TH1	90	92.5	95	%	OUT1 rising, % of V_{OUT1_NOM}
POK Hysteresis	POK_HYS1	—	4	—	%	OUT1 falling, % of V_{OUT1_NOM}
Start-up POK Bypass Threshold	V_{POKB_TH_B1}	–	615	–	mV	PVIN1-OUT1, OUT1 rising, PVIN1 = 3.0V, V_{OUT1_NOM} = 3.3V
Start-up POK Bypass Threshold Hysteresis	V_{POKB_HYS_B1}	—	50	—	mV	OUT1 falling, PVIN1 = 3.0V
Soft-start Rate (switching frequency clock cycles per DAC step)	SSR_00	—	16	—	cycles/ step	SSR[1:0] = 00 - default
	SSR_01	—	32	—		SSR[1:0] = 01
	SSR_10	—	48	—		SSR[1:0] = 10
	SSR_11	—	64	—		SSR[1:0] = 11
Dynamic Voltage Scaling Rate (switching frequency clock cycles per DAC step)	DVSR_00	—	16	—	cycles/ step	DVSR[1:0] = 00 - default
	DVSR_01	—	32	—		DVSR[1:0] = 01
	DVSR_10	—	48	—		DVSR[1:0] = 10
	DVSR_11	—	64	—		DVSR[1:0] = 11
High-Side Peak Current Limit (Cycle by Cycle)	I_{LIM_HS1}	1.2	1.8	2.6	A	—
Current Limit frequency foldback V_OUT1 threshold	V_{TH_FFB1}	—	615	—	mV	—
Hiccup-Mode Short Circuit protection wait time	t_HICCUP	—	3x Soft-start Time	—		—
Low-side Negative Peak Current Limit (FPWM)	I_{LIM_NEG1}	−1.4	−1	−0.8	A	—
Zero Current Detection threshold	I_ZCD1	0	50	120	mA	—
Active Discharge Resistance	R_{DISCH_OUT1}	—	25	—	Ω	DISCH = 1, Enabled when regulator disabled
Note: Not production tested.


T_A = +25°C; VIN = SVIN = PVINx = LVIN = 5V; V_OUT2 = 1.8V, V_OUT3 = 1.1V, V_OUT4 = 1.1V; L2 = L3 = L4 = 1.5 µH; COUT2 = COUT3 = COUT4 = 22 µF, unless otherwise specified. Bold values indicate –40°C ≤ T_J ≤ +125°C.
Parameters	Symbol (x = 2,3,4)	Min.	Typ.	Max.	Units	Conditions
Buck2, buck3, buck4
Input Operating Voltage Range	V_PVINx	2.7	—	5.5	V	—
Output Voltage Range	V_OUTx	0.6	—	1.85	V	—
Output Voltage Step	V_step	—	25	—	mV	—
PVINx Shutdown Current	I_{PVINx_SHDN}	—	0.05	2	µA	Regulator disabled, PVINx = 5V
Operational Quiescent Current AutoPFM (Note 1)	I_{QOP_PFMx}	—	45	—	µA	I_OUTx = 0mA, Auto PFM EN = PWRHLD = LPM = 1, HPM = 0 ΔI_Q for one buck activated
Output Voltage Accuracy, FPWM	ACC_OUT_PWMx	−1	—	+1	%	I_OUTx = 0mA, 0.9V≤V_OUTx ≤1.3V
Output Voltage Accuracy, FPWM	ACC_OUT_PWMx	−1.5	—	+1.5	%	I_OUTx = 0mA, V_OUTx <0.9V or V_OUTx >1.3V
Output Voltage Accuracy, Auto-PFM	ACC_OUT_PFMx	−1	—	+1	%	I_OUTx = 0mA, 0.9V≤V_OUTx ≤1.3V
Output Voltage Accuracy, Auto-PFM	ACC_OUT_PFMx	−1.5	—	+1.5	%	I_OUTx = 0mA, V_OUTx <0.9V or V_OUTx >1.3V
Output Voltage Line Regulation (Note 1)	LINE_REG_PWMx	—	0.03	—	%	I_OUT1 = 0mA, FPWM, V_IN = PVIN1 = SVIN = 3.6V to 5.5V
Output Voltage Line Regulation (Note 1)	LINE_REG_PFMx	—	0.07	—	%	I_OUT1 = 0 mA, Auto PFM, V_IN = PVIN1 = SVIN = 3.6V to 5.5V
Output Voltage Load Regulation (Note 1)	LOAD_REG_PWMx	—	0.3	—	%	I_OUTx = 0A to 1A, FPWM
Output Voltage Load Regulation (Note 1)	LOAD_REG_PFMx	—	0.5	—	%	I_OUTx = 0A to 1A, Auto PFM
Switching Frequency	f_sw	1.8	2	2.2	MHz	FPWM, FSD[1:0] = 00,01
Switching frequency displacement	FSD_10	—	−16.5	—	%	FPWM, FSD[1:0] = 10
Switching frequency displacement	FSD_11	—	16.5	—	%	FPWM, FSD[1:0] = 11
Maximum Duty Cycle	D_MAX	100	—	—	%	Functionality test
Minimum ON Time	T_{ON_MINx}	—	35	—	ns	FPWM
High-Side Switch ON-Resistance	R_DSonPx	—	140	160	mΩ	PVINx = SVIN = 5V
Low-Side Switch ON-Resistance	R_DSonNx	—	120	140	mΩ	PVINx = SVIN = 5V
POK (Power OK) Threshold	POK_THx	90	92.5	95	%	OUTx rising, % of V_OUTx(NOM)
POK hysteresis	POK_HYSx	—	4	—	%	OUTx falling, % of V_OUTx(NOM)
Soft-start Rate (switching frequency clock cycles per DAC step)	SSR_00	—	16	—	cycles / step	SSR[1:0] = 00 - default
	SSR_01	—	32	—		SSR[1:0] = 01
	SSR_10	—	48	—		SSR[1:0] = 10
	SSR_11	—	64	—		SSR[1:0] = 11
Dynamic Voltage Scaling Rate (switching frequency clock cycles per DAC step)	DVSR_00	—	16	—	Cycles step	DVSR[1:0] = 00 - default
	DVSR_01	—	32	—		DVSR[1:0] = 01
	DVSR_10	—	48	—		DVSR[1:0] = 10
	DVSR_11	—	64	—		DVSR[1:0] = 11
High-Side Peak Current Limit (Cycle by Cycle)	I_{LIM_HSx}	1.2	1.8	2.6	A	—
Current Limit Frequency Fold-back V_OUTx Threshold	V_{TH_FFBx}	—	615	—	mV	—
Hiccup-mode Short Circuit Protection Wait Time	t_HICCUP	—	3 × Soft-start Time	—		—
Low-side Negative Peak Current Limit (FPWM)	I_{LIM_NEGx}	−1.4	−1	−0.8	A	—
Zero Current Detection Threshold	I_ZCDx	0	33	120	mA	—
Active Discharge Resistance	R_{DISCH_OUTx}	—	25	—	Ω	DISCH = 1, Enabled when regulator disabled
Note: Not production tested.


T_A = +25°C; VIN = SVIN = PVINx = LVIN = 5V; V_LOUT1,2 = 3.3V; C_LOUT1,2 = 2.2 µF (I_LOUT1,2 ≤ 150 mA) or 4.7 µF (I_LOUT1,2 ≤ 300 mA), unless otherwise specified. Bold values indicate –40°C ≤ T_J ≤ +125°C.
Parameters	Symbol (x = 1,2)	Min.	Typ.	Max.	Units	Conditions
LDO1, LDO2
Input Operating Voltage Range	V_LVIN	2.7	—	5.5	V	—
Output Voltage Range	V_LOUTx	1.2	—	3.7	V	—
Output Voltage Step	V_step	—	50	—	mV	—
Stable Output Capacitor Range (Note 1)	C_LOUTx	2.2	—	20	μF	I_LOUT1,2 ≤ 150 mA – application requirement
Stable Output Capacitor Range (Note 1)	C_LOUTx	4.7	—	20	μF	I_LOUT1,2 ≤ 300 mA – application requirement
LVIN Shutdown Current	I_{LVIN_SHDN}	—	—	2	µA	LDOs disabled, LVIN = 5V
Operational Quiescent Current	I_{LVIN_Qx}	—	40	—	μA	I_LOUT1,2 = 0 mA, one LDO block
Output Voltage Accuracy	ACC_LOUTx	−2	—	+2	%	LVIN = SVIN = 3.6V I_LOUT1,2 = 0.1 mA
Dropout Voltage (Note 2)	V_DOx	—	170	500	mV	I_LOUT1,2 = 300 mA
Output Voltage Line Regulation	LINE_REGx	—	0.024	—	%	LVIN = SVIN = 3.6V to 5.5V I_LOUT1,2 = 0.1 mA
Output Voltage Load Regulation	LOAD_REGx	—	0.3	—	%	I_LOUT1,2 = 0.1 mA to 300 mA
PSRR	PSRRx	—	63	—	dB	f = 1kHz, I_OUT = 20 mA, V_LOUT1,2 = 1.8V, SVIN and LVIN modulated
		—	63	—	dB	f = 1kHz, I_OUT = 20 mA, V_LOUT1,2 = 1.8V, SVIN = 5V, LVIN modulated
		—	46	—	dB	f = 10kHz, I_OUT = 20 mA, V_LOUT1,2 = 1.8V, SVIN and LVIN modulated
		—	47	—	dB	f = 10kHz, I_OUT = 20 mA, V_LOUT1,2 = 1.8V, SVIN = 5V, LVIN modulated
POK (Power OK) Threshold	POK_THL	90	92.3	95	%	LOUT1,2 rising, % of V_LOUT1,2(NOM)
POK Hysteresis	POK_HYSL	—	4	—	%	LOUT1,2 falling, % of V_LOUT1,2(NOM)
Start-up POK Bypass Threshold	V_{POKB_TH_Lx}	—	—	670	mV	LVIN-LOUTx, LOUTx rising, LVIN = 3.0V, V_{LOUTx_NOM} = 3.3V
Start-up POK Bypass Threshold Hysteresis (Note 1)	V_{POKB_HYS_Lx}	—	50	—	mV	LOUTx falling, LVIN = 3.0V
Soft-start Rate (switching frequency clock cycles per DAC step)	SSR_00	—	16	—	cycles / step	SSR[1:0] = 00 – default
	SSR_01	—	32	—		SSR[1:0] = 01
	SSR_10	—	48	—		SSR[1:0] = 10
	SSR_11	—	64	—		SSR[1:0] = 11
Dynamic Voltage Scaling Rate (switching frequency clock cycles per DAC step) – rising only	DVSR_00	—	16	—	cycles / step	DVSR[1:0] = 00 – default
	DVSR_01	—	32	—		DVSR[1:0] = 01
	DVSR_10	—	48	—		DVSR[1:0] = 10
	DVSR_11	—	64	—		DVSR[1:0] = 11
Current Limit	I_{LIM_LOUTx}	310	400	550	mA	SVIN = LVIN = 4.5V, V_LOUT1,2 = 80% of nominal
Active Discharge Resistance	R_{DISCH_LOUTx}	—	25	—	Ω	DISCH = 1, Enabled when regulator disabled and during negative DVS
Notes: Not production tested. Typical value from bench characterization. Maximum value production tested.


T_A = +25°C; VIN = SVIN = PVINx = LVIN = 5V; unless otherwise specified. Bold values indicate –40°C ≤ T_J ≤ +125°C.
Parameters	Symbol	Min.	Typ.	Max.	Units	Conditions
EN Input
Logic HIGH Input Voltage V_IH	V_{IH_EN}	1.5	—	—	V	SVIN = 3.6V-5.5V
Logic LOW Input Voltage V_IL	V_{IL_EN}	—	—	0.4	V	SVIN = 3.6V-5.5V
EN Deglitch Time	t_{DT_EN}	5	10	15	µs	SVIN = 2.7V-5.5V
VSET1, VSETL1, VSETL2 pins
Output Voltage setting Resistor	R_SEL	—	Short to GND	—		VOUTx = OFF
		−1%	0.187	+1%	kΩ	VOUTx = 1.2V
			0.487			VOUTx = 1.25V
			0.976			VOUTx = 1.3V
			1.74			VOUTx = 1.35V
			2.94			VOUTx = 1.4V
			4.87			VOUTx = 1.5V
			8.06			VOUTx = 1.6V
			13			VOUTx = 1.8V
			21			VOUTx = 2.5V
			34			VOUTx = 2.8V
			54.9			VOUTx = 3.0V
			86.6			VOUTx = 3.15V
			140			VOUTx = 3.3V
			226			VOUTx = 3.4V
		—	Short to VIN	—		VOUTx = 3.6V
VSET2, VSET3, VSET4 pins
Output Voltage setting Resistor	R_SEL	—	Short to GND	—		VOUTx = OFF
		−1%	0.187	+1%	kΩ	VOUTx = 0.6V
			0.487			VOUTx = 0.8V
			0.976			VOUTx = 0.9V
			1.74			VOUTx = 1V
			2.94			VOUTx = 1.05V
			4.87			VOUTx = 1.1V
			8.06			VOUTx = 1.15V
			13			VOUTx = 1.2V
			21			VOUTx = 1.25V
			34			VOUTx = 1.275V
			54.9			VOUTx = 1.35V
			86.6			VOUTx = 1.375V
			140			VOUTx = 1.4V
			226			VOUTx = 1.5V
		—	Short to VIN	—		VOUTx = 1.8V
PWRHLD, LPM, HPM Logic Inputs (x = PWRHLD, LPM, HPM)
Logic HIGH Input Voltage V_IH	V_{IH_x}	1.5	—	—	V	SVIN = 3.6V-5.5V
Logic LOW Input Voltage V_IL	V_{IL_x}	—	—	0.4	V	SVIN = 3.6V-5.5V
Input leakage current	I_{lkg_x}	−1	—	1	µA	—
Deglitch Time	t_{DT_x}	—	10	—	µs	—
nRSTO, nSTRTO, nINTO Logic Outputs (x = nRSTO, nSTRTO, nINTO)
Output Voltage LOW V_OL	V_{OL_x}	—	—	0.4	V	SVIN = 3.6V-5.5V, I_OL = 2 mA
Leakage current	I_{lkg_x}	—	—	1	µA	5.5V applied, output driver OFF
SDA, SCL I²C Interface Pins (x = SDA, SCL)
SCL, SDA Logic HIGH Input Voltage V_IH	V_{IH_x}	1.5	—	—	V	SVIN = 3.6V-5.5V
SCL, SDA Logic LOW Input Voltage V_IL	V_{IL_x}	—	—	0.4	V	SVIN = 3.6V-5.5V
Hysteresis of Schmitt trigger inputs	V_{hys_x}	—	0.2	—	V	SVIN = 3.6V-5.5V
SDA, SCL leakage current	I_{lkg_x}	—	—	1	µA	SDA driver OFF, V_SDA = 5.5V, V_SCL = 5.5V
SDA output voltage LOW V_OL	V_OL	—	—	0.4	V	SVIN = 3.6V-5.5V, I_OL = 20 mA
Maximum SCL Clock Frequency	f_SCL	—	1	—	MHz	Functional Test Only
Maximum Pulse Width of input spikes that must be suppressed (Note 1, Note 2)	t_SP	—	50	—	ns	Functional Test Only
Notes: Not production tested. Input filters on the SDA and SCL inputs suppress noise spikes of less than 5 ns.