10.2.4 Netlist Attributes NDC Commands

To set netlist-specific constraints, use Netlist attributes Netlist Design Constraint (NDC) commands. These commands are placed in a Compile Netlist Constraint (*.ndc) file and used by the Libero SoC Compile engine to optimize the post-synthesis netlist.

10.2.4.1 set_mitigation (RTG4 Devices Only)

This command sets the mitigation option on a per-instance basis for RTG4 devices. For the Enhanced Constraint flow, import this NDC command as a Netlist Attributes constraint file (*.ndc) and associate it with Synthesis in the Constraint Manager.

For the Classic Constraint Flow, save the command as a PDC file (*.pdc) and import the *.pdc file into the Project (Design Flow Window > Floorplan Constraints > Import Files). After import, associate the file with Compile (Right-click the PDC file and select Use for Compile).

Important: This NDC/PDC command overrides the project-wide global setting for mitigation option (Project Settings > Device settings > Enable Single Event Transient Mitigation). The global mitigation setting is project-wide and applies to ALL instances in the design that the mitigation option is valid. If you want to override the global setting for certain specific instances in the design (and allow the global setting to remain valid on all other instances), use the set_mitigation command for the specific instances because this command sets the mitigation option on a per-instance basis.
set_mitigation -inst_name <instance_name> -mitigated <value>

Arguments

The following sections describe set_mitigation (RTG4 Devices Only) arguments.

-inst_name <instance_name>

Specifies the name of the instance in the netlist to set the mitigation option. A hierarchical instance name is allowed. The wildcard character "*" in the instance name is also supported. When the mitigation option is set on an instance that contains design elements that can have the mitigation option, all the design elements within that instance are set with this option. This applies to MACC blocks, µSRAM blocks, LSRAM blocks, I/O Flip-Flops, and regular Flip-Flops within that instance.

-mitigated Value

Sets the mitigation value for the instance. The acceptable values for this argument are listed in the following table.

Table 10-83. -mitigated Value
ValueDescription
Yes | ON | true | 1The mitigation option is enabled on this instance. “Yes”, “ON”, “True” are case-insensitive.
No | OFF | false | 0The mitigation option is disabled on this instance. No, OFF, and False are case-insensitive.

Return Value

Returns "0" on success and "1" on failure.

Examples

This example sets the mitigation option on the instance blk1/* globally in the netlist:

set_mitigation -inst_name blk1/* -mitigated yes

After the first command above, to set a different mitigation value on a specific instance, for example, instance FF_1 inside the blk1 instance, use the <-mitigated No> argument as follows:

set_mitigation -inst_name blk1/FF_1 -mitigated No
Note: The last set_mitigation command overrides a previous set_mitigation command, if there is a conflict.

10.2.4.2 set_ioff

This command specifies whether or not a register is combined with an I/O during synthesis/compile. This command is placed in a Compile Netlist Constraint (*.ndc) file and passed to the Libero SoC Compile engine for netlist optimization after synthesis.

set_ioff {<portname>} 
\[-in_reg yes|no] \ 
[-out_reg yes|no] \
[-en_reg yes|no]

Arguments

The following sections describe set_ioff arguments.

portname

Specifies the name of the I/O port to be combined with a register. The port can be an input, output, or inout port.

-in_reg

Specifies whether the input register is combined into the port <portname>. Valid values are “yes” or “no”.

-out_reg

Specifies whether the output register is combined into the port <portname>. Valid values are “yes” or “no”.

-en_reg

Specifies whether the enable register is combined into the port <portname>. Valid values are “yes” or “no”.

Return Value

The command returns “0” on success and “1” on failure.

I/O Register Combining Rules

I/Os are combined with a register to achieve better clock-to-out and input-to-clock timing. When combining these registers at the I/O buffer, some design rules must be met. This feature is supported by all I/O standards. The I/O register combining rules are as follows:

  • Registers combined on the Output and Output Enable must have the same configuration.

    Example: If the output register is DFN1C0, the Output Enable register must also be DFN1C0.

  • All registers (Input, Output, and Output Enable) connected to an I/O must share the same clear (CLR) or preset (PRE) pin
  • If one of the registers has a CLR pin, all the other registers that are candidates for combining in the I/O must have a CLR pin
  • If one of the registers has a PRE pin, all the other registers that are candidates for combining in the I/O must have a PRE pin
  • If one of the registers has neither a CLR nor a PRE pin, all the other registers that are candidates for combining must have neither a CLR nor a PRE pin
  • If the CLR or PRE pins are present, they must have the same polarity
  • If the CLR or PRE pins are present, they must be driven by the same signal (net)
  • The fan-out between an I/O pin (D, Y, or E) and a register must be equal to 1
  • The register pin connected to the I/O must be the 'D' or 'Q' pin
  • Registers connected to an I/O on the Output and Output Enable pins must have the same clock and enable function
  • Both the Output and Output Enable registers must have an E pin (clock enable) or none at all
  • If the E pins are present, they must have the same polarity. The CLK pins must also have the same polarity
  • Input Registers—The I/O must drive the D pin of a register with a fanout of 1
  • Output Registers—The Q pin of the register must drive the D pin of the I/O with a fanout of 1
  • Enable Registers—The Q pin of the register must drive the E pin of the I/O with a fanout of 1
  • Output and Enable Register CLK pins must be driven by the same net with the same polarity to be combined in the same I/O
  • Input, Output and Enable register ALn and SLn must be driven by the same net and the same polarity to combine them into the same I/O

Examples

The following command specifies that for the port my_in_out[1], the output register is combined into the port, but it is not combined into the input register nor the enable register:

set_ioff {my_in_out[1]} –in_reg no –out_reg yes –en_reg no

The following command specifies that for the port my_in_out[19], the enable register is combined into the port, but is not combined into the input register nor the output register:

set_ioff {my_in_out[19]} –in_reg no –out_reg no –en_reg yes

The set_ioff command applies to scalar I/Os only. For an I/O bus, use the for-loop available in Tcl. The following command combines each scalar member of the 32-bit I/O bus DataA with input registers:

for { set i 0 } { i < 32 } { incr i } { set_ioff "DataA\[$i\]" -in_reg yes }

Alternatively, you can use a wild card to include all scalar signals of an I/O bus:

set_ioff {DataA[*]} -in_reg yes

10.2.4.3 set_preserve

This command sets a preserve property on instances before compile. Therefore, the compile will preserve these instances and not combine them.

set_preserve hier_inst_name

Arguments

The following sections describe set_preserve arguments.

hier_inst_name

Specifies the full hierarchical name of the macro in the netlist to preserve.

Exceptions

You must put this command in a PDC constraint file and associate it to Place and Route.

Examples

In some cases, you may want to preserve some instances for timing purposes. For example, you may want registers to be combined with input of a bibuf and keep the output as it is.

If the outbuf of a bi-directional signal test[1] needs to be preserved while inbuf is required to combine with the registers, use the following PDC commands:

set_io test\[1\] -register yes set_preserve test\[31\]

If any internal instance is required to be preserved, use the set_preserve command as shown in the following example:

set_preserve top/inst1 top/inst2