10.2.3 I/O PDC Commands

Arguments

The following sections describe the set_iobank arguments.

bankname

Specifies the name of the bank. I/O banks are numbered 0 through N (bank0, bank1,...bankN). See the datasheet for your device to determine the number of banks.

-vcci vcci_voltage

Sets the input/output supply voltage. You can enter one of the following values:

Table 10-50. -Vcci Values

Vcci Voltage	Compatible Standards
3.3V	LVTTL, LVCMOS 3.3, PCI 3.3, LVPECL
2.5V	LVCMOS 2.5, SSTL2 (Class I and II), LVDS, BUSLVDS, MLVDS, MINILVDS, RSDS
1.8V	LVCMOS 1.8, LPDDRI, LPDDRII, SSTL18I
1.5V	LVCMOS 1.5, SSTL 1.5 (Class I and II), HSTL (Class I and II)
1.2V	LVCMOS 1.2

-vref vref_voltage

Sets the input reference voltage. You can enter one of the following values:

Table 10-51. -vref Values

Vref Voltage	Compatible Standards
1.25V	SSTL2 (Class I and II)
1.0V	SSTL18 (Class I and II), LPDDR (Class I and II)
0.75V	SSTL15 (Class I and II), HSTL (Class I and Class II)

-fixed Value

Specifies if the I/O technologies (vcci and vccr voltage) assigned to the bank are locked. You can enter one of the following values:

Table 10-52. -fixed Values

Value	Description
yes	The technologies are locked.
no	The technologies are not locked.

-vrefpins value

Specifies, if the I/O technologies (vcci and vccr voltage) assigned to the bank are locked. You can enter one of the following values:

Table 10-53. -vrefpins Values

Value	Description
default	Because the VREF pins are not locked, the I/O Bank Assigner can assign a VREF pin.
pinnum	The specified VREF pin(s) are locked if the -fixed option is yes. The I/O Bank Assigner cannot remove locked VREF pins.

-updateiostd Value

Specifies, if the I/O technologies (vcci and vccr voltage) assigned to the bank are locked. You can enter one of the following values:

Table 10-54. -updateiostd Values

Value	Description
yes	If there are I/Os placed on the bank, we keep the placement and change the host to one which is compatible with this bank setting. Check the I/O Attributes to see the one used by the tool.
no	If there are I/Os placed and locked on the bank, the command will fail. If they are placed I/Os they will be unplaced.

Exceptions

Any pins assigned to the specified I/O bank that are incompatible with the default technology are unassigned.

Examples

The following example assigns 3.3V to the input/output supply voltage (vcci) and 1.5V to the input reference voltage (vref) for I/O bank 0.

set_iobank bank0 -vcci 3.3 -vref 1.5

The following example shows that even though you can import a set_iobank command with the -vrefpins argument set to “default”, the exported PDC file shows the specific default pins instead of "default".

Imported PDC file contains:

set_iobank bank3 -vcci 3.3 -vref 1.8 -fixed yes -vrefpins {default}

Exported PDC file contains:

set_iobank bank3 -vcci 3.3 -vref 1.8 -fixed yes -vrefpins {N3 P8 M8}

See Also

• "reset_io"
• "reset_iobank"

Arguments

The following sections describe reset_io arguments.

portname

Specifies the port name of the I/O macro to be reset. You can use the following wild card characters in port names:

Table 10-55. portname Characteristics

Wild Card	What It Does
\	Interprets the next character as a non-special character
?	Matches any single character
*	Matches any string

-attributes Value

Preserve or not preserve the I/O attributes during incremental flow. The following table shows the acceptable values for this argument:

Table 10-56. -attributes Values

Value	Description
yes	Unassigns all of the I/O attributes and resets them to their default values.
no	Unassigns only the port.

Exceptions

None.

Examples

Resets the I/O macro "a" to the default I/O attributes and unassigns it.

Resets all I/O macros beginning with "b" to the default I/O attributes and unassigns them.

Only unassigns port b from its location.

See Also

• "set_io (SmartFusion 2 and IGLOO 2)"
• "set_io (RTG4 only)"

Arguments

The following section describes reset_iobank arguments.

bankname

Specify, if the I/O bank must be reset to the default technology. I/O banks are numbered 0-7 (bank0, bank1, …, bank7).

Exceptions

Any pins that are assigned to the specified I/O bank but are incompatible with the default technology are unassigned.

Examples

The following example resets the I/O bank 4 to the default technology:

reset_iobank bank4

See Also

• "set_iobank"

Arguments

The following section describes reserve arguments.

-pinname "list of package pins"

Specify the package pin name(s) to reserve. You can reserve one or more pins.

Exceptions

None.

Examples

reserve -pinname "F2"
reserve -pinname "F2 B4 B3"
reserve -pinname "124 17"

See Also

• "unreserve"

Arguments

The following section describes set_io (SmartFusion 2 and IGLOO 2) arguments. The attributes below are case sensitive.

portname

Specify the portname of the I/O macro.

-iostd Value

Sets the I/O standard for this macro. Choosing a standard allows the software to set other attributes, such as the slew rate and output loading. If the voltage standard used with the I/O is not compatible with other I/Os in the I/O bank, then assigning an I/O standard to a port will invalidate its location and automatically unassign the I/O.

The following table lists the supported I/Os by Bank type.

Table 10-57. -iostd Values

MSIOD	MSIO	DDRIO
—	LVTTL	—
—	LVCMOS33	—
—	PCI	—
—	LVPECL (Input ONLY)	—
—	LVDS33	—
LVCMOS12	LVCMOS12	LVCMOS12
LVCMOS15	LVCMOS15	LVCMOS15
LVCMOS18	LVCMOS18	LVCMOS18
LVCMOS25	LVCMOS25	LVCMOS25
SSTL2I	SSTL2I	SSTL2I (DDR1)
—	STL2II	SSTL2II (DDR1)
SSTL18I	SSTL18I	SSTL18I (DDR2)
—	SSTL18II	SSTL18II (DDR2)
HSTLI	HSTLI	HSTLI
—	—	HSTLII
—	—	SSTL15I (DDR3)
—	—	SSTL15II (DDR3)
—	—	LPDDRI
—	—	LPDDRII
LVDS	LVDS	—
RSDS	RSDS	—
MINILVDS	MINILVDS	—
BUSLVDS (Input ONLY)	BUSLVDS	—
MLVDS (Input ONLY)	MLVDS	—

I/O standards support for single and differential I/Os is shown in the following table.

Table 10-58. I/O Standards for Single and Differential I/Os

Value	Single	Differential	Description
LVTTL	X	—	(Low-Voltage TTL) A general purpose standard (EIA/JESDSA) for 3.3V applications. It uses an LVTTL input buffer and a push-pull output buffer.
LVCMOS33	X	—	(Low-Voltage CMOS for 3.3V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 3.3V applications.
LVCMOS25	X	—	(Low-Voltage CMOS for 2.5V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5V applications.
LVCMOS18	X	—	(Low-Voltage CMOS for 1.8V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer.
LVCMOS15	X	—	(Low-Voltage CMOS for 1.5V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer.
LVCMOS12	X	—	(Low-Voltage CMOS for 1.2V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 1.2V applications.
LVDS	—	X	A moderate-speed differential signaling system, in which the transmitter generates two different voltages which are compared at the receiver. It requires that one data bit be carried through two signal lines; therefore, you need two pins per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV.
LVDS33	—	X	LVDS for 3.3V
BUSLVDS	—	X	2.5V BUSLVDS
MLVDS	—	X	—
MINILVDS	—	X	—
RSDS	—	X	—
LVPECL (only for inputs)	—	X	PECL is another differential I/O standard. It requires that one data bit is carried through two signal lines; therefore, two pins are needed per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 850 mV. When the power supply is 3.3V, it is commonly referred to as Low-Voltage PECL (LVPECL).
PCI	—	—	(Peripheral Component Interface) Specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be 5V compliant for most families.
PCIX	—	—	(Peripheral Component Interface Extended) An enhanced version of the PCI specification that can support higher average bandwidth; it increases the speed that data can move within a computer from 66 MHz to 133 MHz. PCI-X is backward-compatible, which means that devices can operate at conventional PCI frequencies (33 MHz and 66 MHz). PCI-X is also more Fault tolerant than PCI.
HSTLI	X	X	(High-Speed Transceiver Logic) A general purpose, high-speed 1.5V bus standard (EIA/JESD8-6). It has four classes; Microchip® SoC supports Class I and II. It requires a differential amplifier input buffer and a push- pull output buffer.
HSTLII	X	X	(High-Speed Transceiver Logic) A general purpose, high-speed 1.5V bus standard (EIA/JESD8-6). It has four classes; Microchip SoC supports Class I and II. It requires a differential amplifier input buffer and a push-pull output buffer.
SSTL2I	X	X	(Stub Series Terminated Logic for 2.5V) A general purpose 2.5V memory bus standard (JESD8-9). It has two classes; Microchip SoC supports both. It requires a differential amplifier input buffer and a push-pull output buffer.
SSTL2II	X	X	See SSTL2I above.
SSTL15I	X	X	(Stub Series Terminated Logic for 1.5V) A general purpose 1.5V memory bus standard (JESD8-9). It has two classes; Microchip SoC supports both. It requires a differential amplifier input buffer and a push-pull output buffer.
SSTL15II	X	X	See SSTL15I
SSTL18II	X	X	(Stub Series Terminated Logic for 1.8V) A general-purpose 1.8V memory bus standard (JESD8-9). It has two classes; Microchip SoC supports both. It requires a differential amplifier input buffer and a push-pull output buffer.

-pre_emphasis Value

The pre-emphasis rate is the amount of rise or fall time an input signal takes to get from logic low to logic high or vice versa. It is commonly defined to be the propagation delay between 10% and 90% of the signal's voltage swing. Possible values are shown in the following table. The output buffer has a programmable slew rate for both high-to-low and low-to-high transitions. The low rate is incompatible with 3.3V PCI requirements.

Table 10-59. -pre_emphasis Value

Value	Description
NONE	Sets to none (default)
MIN	Sets to minimum
MEDIUM	Sets to medium
MAX	Sets to maximum

-lpe Value

Sets the state at which your device exits from Low Power mode. Possible values are shown in the following table.

Table 10-60. -lpe Value

Value	Description
OFF	Default; no LPE set
Wake_on_Change	Exits from Low Power mode on change
Wake_on_0	Exits from Low Power mode on 0
Wake_on_1	Exits from Low Power mode on 1

-ff_io_state Value

Preserves the previous state of the I/O. By default, all the I/Os become striated, when the device goes into Flash*Freeze mode. (A tristatable I/O is an I/O with three output states: high, low, and high-impedance.) You can override this default using theFF_IO_STATE attributes. When you set this attribute to LAST_VALUE, the I/O remains in the same state in which it was functioning before the device went into Flash*Freeze mode. Possible values are shown in the following table.

Table 10-61. -ff_io_state Value

Value	Description
TRISTATE	Sets the I/O to tri-state (default).
LAST_VALUE	Preserves the previous state of the I/O.

-out_drive Value

Sets the strength of the output buffer to 2, 4, 6, 8, 10, 12, 16, or 20 in mA, weakest to strongest. The list of I/O standards for which you can change the output drive and the list of values you can assign for each I/O standard is family-specific. Not all I/O standards have a selectable output drive strength. Also, each I/O standard has a different range of legal output drive strength values. The values you can choose from depend on which I/O standard you have specified for this command. See the Slew and Out_drive Settings table under "Exceptions" in this topic for possible values. The following table lists the acceptable values.

Table 10-62. -out_drive Value

Value	Description
2	Sets the output drive strength to 2 mA
4	Sets the output drive strength to 4 mA
6	Sets the output drive strength to 6 mA
8	Sets the output drive strength to 8 mA
10	Sets the output drive strength to 10 mA
12	Sets the output drive strength to 12 mA
16	Sets the output drive strength to 16 mA
20	Sets the output drive strength to 20 mA

-slew Value

Sets the output slew rate. Slew control affects only the falling edges for some families. Slew control affects both rising and falling edges. Not all I/O standards have a selectable slew. Whether you can use the slew attribute depends on which I/O standard you have specified for this command.

See the Slew and Out_drive Settings table under Exceptions in this topic. The following table lists the acceptable values for the -slew attribute.

Table 10-63. -slew Value

Value	Description
SLOW	Sets the I/O slew to slow.
MEDIUM	Sets the I/O slew to medium.
MEDIUM_FAST	Sets the I/O slew to medium fast.
FAST	Sets the I/O slew to fast.

-res_pull Value

Allows you to include a weak resistor for either pull-up or pull-down of the input buffer or the output buffer. Not all I/O standards have a selectable resistor pull option. The following table shows the acceptable values for the -res_pull attribute.

Table 10-64. -res_pull Value

Value	Description
up	Includes a weak resistor for pull-up of the input buffer.
down	Includes a weak resistor for pull-down of the input buffer.
none	Does not include a weak resistor. This is the default value.

-schmitt_trigger Value

Specifies whether this I/O has an input Schmitt Trigger. The Schmitt Trigger introduces hysteresis on the I/O input. This allows very slow moving or noisy input signals to be used with the part without false or multiple I/O transitions taking place in the I/O. The following table lists the acceptable values for the - schmitt_trigger attribute.

Table 10-65. -schmitt_trigger Value

Value	Description
ON	Turns the Schmitt Trigger ON.
OFF	Turns the Schmitt Trigger OFF.

-in_delay Value

Specifies whether this I/O has an input delay. You can specify an input delay between 0 and 63. The input delay is not a delay value but rather a selection from 0 to 63. The actual value is a function of the operating conditions and is automatically computed by the delay extractor when a timing report is generated. The following table lists the acceptable values for the -in_delay attribute.

Table 10-66. -in_delay Value

Value	Description
OFF	This I/O does not have an input delay.
0	Sets the input delay to 0.
1	Sets the input delay to 1.
2	Sets the input delay to 2.
...	...
63	Sets the input delay to 63.

-odt_static Value

On-Die Termination (ODT) is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board. The following table lists the possible values.

Table 10-67. -odt_static Value

Value	Description
ON	Yes, the termination resistor for impedance matching is located inside the chip
OFF	No, the termination resistor is on the printed circuit board

-odt_imp Value

ODT is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board.

Port Configuration (PC) bits are static configuration bits set during programming to configure the I/O(s) as per your choice. See your device data sheet for a full range of possible values.

-ff_io_avail Value

Indicates the I/O is available in Flash*Freeze mode. The following table lists the possible values.

Table 10-68. -ff_io_avail Value

Value	Description
yes	I/O is available in Flash*Freeze mode.
no	By default, I/O is unavailable in Flash*Freeze mode.

-pinname package_pin

Specifies the package pin name(s) on which to place the I/O.

-fixed Value

Specifies whether the pin is locked or unlocked.

Table 10-69. -fixed Value

Value	Description
yes	The location of this port is locked.
no	The location of this port is unlocked.

-out_load Value

Sets the output load (in pF) of output signals. The default is 5.

Direction: Output

Examples

set_io PAD \
-PINNAME A2 \
-FIXED yes \
-FF_IO_STATE LAST_VALUE \
set_io PAD_0 \
-pinname A8 \
-fixed yes \
-IN_DELAY 6 \
-LPE Wake_On_Change \
-RES_PULL Down \
-SCHMITT_TRIGGER On \
set_io PAD_3 \
-OUT_DRIVE 6 \
-OUT_LOAD 52 \

See Also

• "reset_io"

Arguments

The following section describes set_io (RTG4 only) arguments.

portname

Specifies the portname of the I/O macro.

-direction Value

Specifies the direction of the I/O ports. Valid values are input, output, and inout.

-iostd Value

Sets the I/O standard for this macro. Choosing a standard allows the software to set other attributes, such as the slew rate and output loading. If the voltage standard used with the I/O is not compatible with other I/Os in the I/O bank, then assigning an I/O standard to a port will invalidate its location and automatically unassign the I/O.

The following table lists a list of supported I/Os by Bank type.

Table 10-70. -iostd Value

MSIOD	MSIO	DDRIO
—	LVTTL	—
—	LVCMOS33	—
—	PCI	—
—	LVPECL (Input ONLY)	—
—	LVDS33	—
LVCMOS12	LVCMOS12	LVCMOS12
LVCMOS15	LVCMOS15	LVCMOS15
LVCMOS18	LVCMOS18	LVCMOS18
LVCMOS25	LVCMOS25	LVCMOS25
SSTL2I	SSTL2I	SSTL2I (DDR1)
SSTL2II	STL2II	SSTL2II (DDR1)
SSTL18I	SSTL18I	SSTL18I (DDR2)
SSTL18II	SSTL18II	SSTL18II (DDR2)
HSTLI	HSTLI	HSTLI
—	—	HSTLII
—	—	SSTL15I (DDR3) Only for IOs used by FDDR
—	—	SSTL15II (DDR3) Only for I/OS used by FDDR
—	—	LPDDRI
—	—	LPDDRII
LVDS	LVDS	—
RSDS	RSDS	—
MINILVDS	MINILVDS	—
BUSLVDS (Input ONLY)	BUSLVDS	—
MLVDS (Input ONLY)	MLVDS	—

I/O standards support for single and differential I/Os is shown in the following table.

Table 10-71. I/O Standards for Single and Differential I/Os

Value	Single	Differential	Description
LVTTL	X	—	(Low-Voltage TTL) A general purpose standard (EIA/ JESDSA) for 3.3V applications. It uses an LVTTL input buffer and a push-pull output buffer.
LVCMOS33	X	—	(Low-Voltage CMOS for 3.3V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 3.3V applications.
LVCMOS25	X	—	(Low-Voltage CMOS for 2.5V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5V applications.
LVCMOS18	X	—	(Low-Voltage CMOS for 1.8V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer.
LVCMOS15	X	—	(Low-Voltage CMOS for 1.5V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer.
LVCMOS12	X	—	(Low-Voltage CMOS for 1.2V) An extension of the LVCMOS standard (JESD8-5) used for general purpose 1.2V applications. This I/O standard is supported only in ProASIC®3L and the IGLOO® family of devices.
LVDS	—	X	A moderate-speed differential signaling system, in which the transmitter generates two different voltages which are compared at the receiver. It requires that one data bit be carried through two signal lines. Therefore, you need two pins per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV.
LVDS33	—	X	LVDS for 3.3V
BUSLVDS	—	X	2.5V BUSLVDS
MLVDS	—	X	—
MINILVDS	—	X	—
RSDS	—	X	—
LVPECL (only for inputs)	—	X	PECL is another differential I/O standard. It requires that one data bit is carried through two signal lines; therefore, two pins are needed per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 850 mV. When the power supply is 3.3V, it is commonly referred to as LVPECL.
HSTLI	X	X	High-Speed Transceiver Logic Class I. A general- purpose, high-speed 1.5V bus standard (EIA/JESD 8-6). It has four classes; Microchip® SoC supports Class I and Class II. It requires a differential amplifier input buffer and a push-pull output buffer.
HSTLII	X	X	High-Speed Transceiver Logic Class II. A general- purpose, high-speed 1.5V bus standard (EIA/JESD8-6). It has four classes; Microchip SoC supports Class I and Class II. It requires a differential amplifier input buffer and a push-pull output buffer.
HSTL18I	X	X	High-Speed Transceiver Logic 1.8V Class I. A general- purpose, high-speed 1.8V bus. It has four classes; Microchip SoC supports Class I and Class II. It requires a differential amplifier input buffer and a push-pull output buffer.
HSTL18II	X	X	High-Speed Transceiver Logic 1.8V Class II. A general- purpose, high-speed 1.8V bus. It has four classes; Microchip SoC supports Class I and Class II. It requires a differential amplifier input buffer and a push-pull output buffer.
SSTL2I	X	X	(Stub Series Terminated Logic for 2.5V) A general- purpose 2.5V memory bus standard (JESD8-9). It has two classes: Class I and Class II; Microchip SoC supports both. It requires a differential amplifier input buffer and a push-pull output buffer.
SSTL2II	X	X	See SSTL2I above.
SSTL15I	X	X	Stub Series Terminated Logic for 1.5V Class I. A general purpose 1.5V memory bus standard (JESD8-9). It has two classes: Class I and Class II; Microchip supports both. It requires a differential amplifier input buffer and a push-pull output buffer.
SSTL15II	X	X	Stub Series Terminated Logic for 1.5V Class II. See SSTL15I above.
SSTL18I	X	X	Stub Series Terminated Logic for 1.8V Class I. A general purpose 1.8V memory bus standard (JESD8-9). It has two classes; Microchip SoC supports both. It requires a differential amplifier input buffer and a push- pull output buffer.
SSTL18II	X	X	Stub Series Terminated Logic for 1.8V Class II. A general purpose 1.8V memory bus standard (JESD8-9). It has two classes; Microchip SoC supports both. It requires a differential amplifier input buffer and a push- pull output buffer.
LPDDRI	X	X	—
LPDDRII	X	X	—

-pre_emphasis Value

The pre-emphasis rate is the amount of rise or fall time an input signal takes to get from logic low to logic high or vice versa. It is commonly defined to be the propagation delay between 10% and 90% of the signal's voltage swing. Possible values are shown in the following table. The output buffer has a programmable slew rate for both high-to-low and low-to-high transitions.

Table 10-72. -pre_emphasis Value

Value	Description	Applicable to I/O Standards
NONE	Sets to none (default)	LVDS, RSDS
MIN	Sets to minimum	LVDS, RSDS
MEDIUM	Sets to medium	RSDS only
MAX	Sets to maximum	LVDS, RSDS

-out_drive Value

Sets the strength of the output buffer to 2, 4, 6, 8, 10, 12, 16, or 20 in mA, weakest to strongest. The list of I/O standards for which you can change the output drive and the list of values you can assign for each I/O standard is family-specific and I/O Bank Type -specific. Not all I/O standards have a selectable output drive strength. Also, each I/O standard has a different range of legal output drive strength values. The values you can choose from depend on which I/O standard you have specified for this command. The following table lists the acceptable values.

Table 10-73. -out_drive Value

Value (mA)	Description
2	Sets the output drive strength to 2 mA
4	Sets the output drive strength to 4 mA
6	Sets the output drive strength to 6 mA
8	Sets the output drive strength to 8 mA
10	Sets the output drive strength to 10 mA
12	Sets the output drive strength to 12 mA
16	Sets the output drive strength to 16 mA
20	Sets the output drive strength to 20 mA

Table 10-74. I/O Standards

I/O Standard	User -set Valid Output Drive Values (mA) Per I/O Bank Type			Valid Output Drive Value for Die
LVTTL	MSIO	MSIOD	DDRIO	—
	2	—	—	2
	4	—	—	4
	8	—	—	8
	12	—	—	12
	16	—	—	16
LVCMOS33	2	—	—	2
	4	—	—	4
	8	—	—	8
	12	—	—	12
	16	—	—	16
LVCMOS12	2	2	2	2
	4	4	4	4
	—	6	6	6
LVCMOS15	2	2	2	2
	4	4	4	4
	6	6	6	6
	8	—	8	8
	—	—	10	10
	—	—	12	12
LVCMOS18	2	2	2	2
	4	4	4	4
	6	6	6	6
	8	8	8	8
	10	—	10	10
	12	—	12	12
	—	—	16	16

-out_load Value

Sets the output load (in pF) of output signals.

-slew Value

Sets the output slew rate. Slew control affects only the falling edges for some families. Slew control affects both rising and falling edges. Not all I/O standards have a selectable slew. Whether you can use the slew attribute depends on which I/O standard you have specified for this command.

The following table lists the acceptable values for the -slew attribute.

Table 10-75. -slew Value

Value	Description	I/O Standard	I/O Bank Type
SLOW	Sets the I/O slew to slow	LVCMOS12, LVCMOS15, LVCMOS18	MSIO, MSIOD, DDRIO
MEDIUM	Sets the I/O slew to medium	LVCMOS12, LVCMOS15, LVCMOS18	DDRIO
FAST	Sets the I/O slew to fast	LVCMOS12, LVCMOS15	DDRIO

-res_pull Value

Allows you to include a weak resistor for either pull-up or pull-down of the input buffer or the output buffer. Not all I/O standards have a selectable resistor pull option. The following table shows the acceptable values for the -res_pull attribute for different I/O Standard and I/O Bank combinations.

Table 10-76. -res_pull Value

Value	I/O Standard	I/O Bank Type	Description
up	LVTTL, LVCMOS33 PCI	MSIO	Includes a weak resistor for pull- up of the input buffer
	LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25	MSIO/MSIOD/ DDRIO	—
down	LVTTL, LVCMOS33 PCI	MSIO	Includes a weak resistor for pull- down of the input buffer
	LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25	MSIO/MSIOD/ DDRIO	—
none	LVTTL, LVCMOS33 PCI	MSIO	Does not include a weak resistor (Default value)
	LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25	MSIO/MSIOD/ DDRIO	—

-schmitt_trigger Value

Specifies whether this I/O has an input Schmitt Trigger. The Schmitt Trigger introduces hysteresis on the I/O input. This allows very slow moving or noisy input signals to be used with the part without false or multiple I/O transitions taking place in the I/O. The following table shows the acceptable values for the -schmitt_trigger attribute.

Table 10-77. -schmitt_trigger Value

Value	Description
ON	Turns the Schmitt Trigger ON.
OFF	Turns the Schmitt Trigger OFF (Default value).

The applicable valid values are dependent on the I/O Standard and the I/O Bank Type.

Table 10-78. I/O Standard and the I/O Bank Type

I/O Standard	I/O Bank Type
LVTTL	MSIO	MSIOD	DDRIO
	OFF/ON	N/A	N/A
LVCMOS33	OFF/ON	N/A	N/A
PCI	OFF/ON	N/A	N/A
LVCMOS12	OFF/ON	OFF/ON	OFF/ON
LVCMOS15	OFF/ON	OFF/ON	OFF/ON
LVCMOS18	OFF/ON	OFF/ON	OFF/ON
LVCMOS25	OFF/ON	OFF/ON	OFF/ON

-input_delay Value

Specifies whether this I/O has an input delay. You can specify an input delay between 0 and 63. The input delay is not an absolute delay value but rather a selection from 0 to 63. The actual value is a function of the operating conditions and is automatically computed by the delay extractor when a timing report is generated. The following table shows the acceptable values for the -input_delay attribute.

Table 10-79. -input_delay Value

Value	Description
OFF	This I/O does not have an input delay (Default value)
0	Sets the input delay to 0
1	Sets the input delay to 1
2	Sets the input delay to 2
...	...
63	Sets the input delay to 63

-odt_static Value

ODT is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board. Possible value are listed in the following table.

Note: ODT is not allowed for 2.5V or higher single-ended signals. It is allowed for differential signals.

Table 10-80. -odt_static Value

Value	Description
ON	Yes, the termination resistor for impedance matching is located inside the chip.
OFF	No, the termination resistor is on the printed circuit board (Default value).

The valid value for each I/O Standard and I/O Bank Type combination is listed in the following table.

Table 10-81. I/O Standard and I/O Bank Type

I/O Standard	I/O Bank Type
	MSIO	MSIOD	DDRIO
LVPECL	OFF/ON	N/A	N/A
LVDS33	OFF/ON	N/A	N/A
SSTL18I (DDR2)	OFF/ON	OFF/ON	OFF/ON
SSTL18II (DDR2)	OFF/ON	OFF/ON	OFF/ON
HSTL18I	OFF/ON	OFF/ON	OFF/ON
HSTL18II	N/A	N/A	OFF/ON
HSTLI	OFF	OFF	OFF/ON
HSTLII	OFF	OFF	OFF/ON
SSTL15I (DDR3)	N/A	N/A	OFF/ON
SSTL15II (DDR3)	N/A	N/A	OFF/ON
LPDDRI	N/A	N/A	OFF/ON
LPDDRII	N/A	N/A	OFF/ON
LVDS	OFF/ON	OFF/ON	N/A
RSDS	OFF/ON	OFF/ON	N/A
MINILVDS	OFF/ON	OFF/ON	N/A
BUSLVDS	OFF/ON	OFF/ON	N/A
MLVDS	OFF/ON	OFF/ON	N/A

-odt_dynamic Value

This option is not supported for “ES” devices. It is supported only for production devices. This option is used to opt in or out of the dynamic odt set on a bank. Possible value are listed in the table below.

Value	Description
ODT_STATIC = ON ODT_DYNAMIC = ON	Illegal
ODT_STATIC = ON ODT_DYNAMIC = OFF	The ODT resistor is always turned ON.
ODT_STATIC = OFF ODT_DYNAMIC = OFF	The ODT resistor is always turned OFF.
ODT_STATIC = OFF ODT_DYNAMIC = ON	The ODT resistor is ON or OFF based on the ODT Dynamic bank setting.

The following I/O standards are supported:

LVDS, RSDS, MINILVDS, LVPECL, HSTLI, HSTLII, SSTL15I, SSTL15II, SSTL18I, SSTL18II, HSTL18I, HSTL18II, LPDDRI, LPDDRII

-odt_imp Value

ODT is the technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip instead of on a printed circuit board. The valid value for each I/O Standard and I/O Bank type is listed in the table below. When the value for an I/O standard is not listed, the impedance value is fixed for the specific I/O standard and is not user- selectable.

Table 10-82. -odt_imp Value

I/O Standard	I/O Bank Type
	MSIO	MSIOD	DDRIO
SSTL18I (DDR2)	50 75 150	50 75 150	50 75 150
SSTL18II (DDR2)	50 75 150	50 75 150	50 75 150
HSTL18I	50 75 150	50 75 150	50 75 150
HSTL18II	—	—	50 75 150
LPDDRI	—	—	50 75 150
LPDDRII	—	—	50 75 150
SSTL15I (DDR3)	—	—	20 30 40 60 120
SSTL15II (DDR3)	—	—	20 30 40 60 120

PC bits are static configuration bits set during programming to configure the IO(s) as per your choice. See your device data sheet for a full range of possible values.

Examples

set_io IO_in\[2\] -iostd LVCMOS25 \
-slew slow \
-schmitt_trigger off \
-input_delay off \

See Also

• "reset_io"

Arguments

The following section describes unreserve arguments.

-pinname "list of package pins"

Specifies the package pin name(s) to unreserve.

Exceptions

None.

Examples

unreserve -pinname "F2" 
unreserve -pinname "F2 B4 B3" 
unreserve -pinname "124 63"

See Also

• "reserve"