Special

16.2.5.1 FCEND_BUFF

Buffer, driven by the FCO pin of the last macro in the Carry-Chain.

Figure 16-151. FCEND_BUFF

Table 16-324. FCEND_BUFF I/O
Input	Output
A	Y

Table 16-325. FCEND_BUFF Truth Table
A	Y
0	0
1	1

16.2.5.2 FCINIT_BUFF

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Buffer, used to initialize the FCI pin of the first macro in the Carry-Chain.

Figure 16-152. FCINIT_BUFF

Table 16-326. FCINIT_BUFF I/O
Input	Output
A	Y

Table 16-327. FCINIT_BUFF Truth Table
A	Y
0	0
1	1

16.2.5.3 FLASH_FREEZE

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The Flash_Freeze macro is a special-purpose macro that provides information on when the chip is about to go into Flash* Freeze mode to allow the user to perform any housekeeping needed before the device enters into Flash*Freeze mode. The macro has two outputs:

FF_TO_START—This signal goes high when the FPGA is about to go into Flash*Freeze mode.
FF_DONE—This signal goes high when the FPGA has successfully entered Flash*Freeze mode.

For more information about this macro, see the UG0450: SmartFusion2 and IGLOO2 System Controller User Guide and the SmartFusion2 and IGLOO2 FPGA Low-Power Design User Guide .

There is no simulation model for this macro. The two outputs remain low during simulation because Flash-Freeze is not supported during simulation.

16.2.5.4 LIVE_PROBE_FB

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This is a special-purpose macro that feeds the live probe signals back to the fabric. You can connect the PROBE_A/PROBE_B signals to any unused I/O during design generation. This is useful if PROBE_A/PROBE_B cannot be brought out for debugging due to board limitations. PROBE_A and PROBE_B pins must be reserved, if LIVE_PROBE_FB macro is used. This macro is not supported in simulation.

16.2.5.5 RCOSC_1MHZ

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The RCOSC_1 MHZ oscillator is an RC oscillator that provides a free running clock of 1 MHz frequency.

Figure 16-155. RCOSC_1 MHZ

16.2.5.6 RCOSC_1MHZ_FAB

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The RCOSC_1 MHZ_FAB macro provides an interface from the RCOSC_1 MHZ oscillator to fabric logic.

Figure 16-156. RCOSC_1 MHZ_FAB

16.2.5.7 RCOSC_25_50MHZ

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The RCOSC_25_50 MHZ oscillator is an RC oscillator that provides a free running clock of 25 MHz (at 1.0V supply voltage) or 50 MHz (at 1.2V supply voltage).

Figure 16-157. RCOSC_25_50MHZ

16.2.5.8 RCOSC_25_50 MHZ_FAB

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The RCOSC_25_50MHZ_FAB macro provides an interface from the RCOSC_25_50MHZ oscillator to fabric logic.

Figure 16-158. RCOSC_25_50 MHZ_FAB

16.2.5.9 SYSCTRL_RESET_STATUS

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This special-purpose macro checks the status of the System Controller. The RESET_STATUS output port goes high when the System Controller is in reset mode. To enable this, select the "System Controller Suspend Mode" option in the "Device Settings" under Libero's Project Settings.

Important: This macro does not support simulation. To simulate the System Controller suspend mode, add the following pseudo-code to the simulation testbench:

At simulation time t = 0, set RESET_STATUS = 0.
X¹ μs after observing POWER_ON_RESET_N = 1, set RESET_STATUS = 1 to indicate that the system controller has entered suspend mode.

¹The current supported simulation is a fast simulation. In this environment X = 12.12 μs. The current supported simulation is a fast simulation where X = 12.12 μs. For more information about the system-level simulations that include power supply ramp time and actual delay times, see power-up to functional times in the DS0128: IGLOO2 and SmartFusion2 Datasheet . In this environment, X = T_VDD2OUT + 5 μs or X = T_DEVRST2OUT + 5 μs.

16.2.5.10 SYSRESET

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SYSRESET is a special-purpose macro. The Output POWER_ON_RESET_N goes low at power-up and when DEVRST_N goes low.

Table 16-328. SYSRESET I/O
Input	Output
DEVRST_N	POWER_ON_RESET_N

Table 16-329. SYSRESET TRUTH TABLE
DEVRST_N	POWER_ON_RESET_N
0	0
1	1

16.2.5.11 XTLOSC

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The crystal oscillator provides up to a 20 MHz clock signal. Physically, it requires connection to an external crystal. However, for simulation purposes the XTL pin provides a clock signal running at the desired input frequency. MODE is a two-bit configuration parameter that specifies the frequency range, as shown in the following table.