17.1.9.1 Derive Constraints Tcl Commands

The derive_constraints utility helps you derive constraints from the RTL or the configurator outside the Libero SoC design environment. To generate constraints for your design, you need the User HDL, Component HDL, and Component Constraints files. The SDC component constraints files are available under <project>/component/work/<component name>/<instance_name>/ directory after component configuration and generation.

Each component constraint file consists of the set_component tcl command (specifies the component name) and the list of constraints generated after configuration. The constraints are generated based on the configuration and are specific to each component.

Component Constraint File for the PF_CCC Core

Here is an example of a component constraint file for the PF_CCC core: 
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# Microchip Corp.
# Date: 2021-Oct-26 04:36:00
# Base clock for PLL #0
create_clock -period 10 [ get_pins { pll_inst_0/REF_CLK_0 } ]
create_generated_clock -divide_by 1 -source [ get_pins { pll_inst_0/REF_CLK_0 } ] 
-phase 0 [ get_pins { pll_inst_0/OUT0 } ]
Here, create_clock and create_generated_clock are reference and output clock constraints respectively, which are generated based on the configuration.