6 Introduction

PolarFire® FPGA Block Flow is a bottom-up design methodology that enables you to use design blocks (components) as building blocks for your top-level designs. These building blocks might have already completed layout, and been optimized for timing and power performance for a specific Microchip device. Using these blocks in the top-level designs can reduce design time and improve timing and power performance.

Block offers unique advantages that allow you to:

  • Focus on the timing of primary blocks and ensure that timing requirements are met across these blocks before integrating with top-level blocks.

  • Re-use the block without reoptimizing for timing closure to ensure that changes in other blocks do not impact your block.

  • Re-use a block in multiple designs.
  • Reduce the verification time by re-verifying the updated part of the design only.

Supported Device Families

The following table lists the family of devices that Libero® SoC supports. This guide covers all these device families. However, some information in this guide might apply to certain device families only. In this case, such information is clearly identified.
Table 6-1. Device Families Supported by Libero SoC
Device FamilyDescription
PolarFire®PolarFire FPGAs deliver the industry’s lowest power at mid-range densities with exceptional security and reliability.
PolarFire SoCPolarFire SoC is the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster, and a deterministic L2 memory subsystem enabling Linux and real-time applications.
SmartFusion®2SmartFusion2 addresses fundamental requirements for advanced security, high reliability, and low power in critical industrial, military, aviation, communications, and medical applications.
IGLOO®2IGLOO2 is a low-power mixed-signal programmable solution.
RTG4™RTG4 is Microchip's family of radiation-tolerant FPGAs.