7 Introduction
(Ask a Question)The SmartDesign tool is a visual block-based design creation and entry tool for instantiating, configuring, and connecting Microchip IPs, user-generated IPs, and custom and glue-logic HDL modules. The tool provides a canvas for stitching together the various design components.
The resulting HDL from the SmartDesign tool is a Design-Rule-Checked (DRC) and synthesis-ready HDL file. A generated SmartDesign can be the entire FPGA design or a component subsystem to be reused in a larger design.
The SmartDesign canvas instantiates the following design objects:
- Microchip IP cores
- User-generated or third-party IP cores
- HDL modules
- HDL parameterized core modules
- Basic macros
- Other SmartDesign components
- Reusable design blocks published from the Libero® SoC Design Suite
The SmartDesign tool provides the following features for effortless design creation and visualization:
- Addition of synthesis attributes to design objects
- Visualization of the memory map of the design
- Smart Search and Connect tool for fast design look-up and connectivity for complex designs
- Smart Search and Filter to create focused cones of the design on the canvas