1.1 Libero SoC Design Suite v2025.1 Welcome Page

RTG4

• PLL calibration updates for RTG4FCCCECALIB v2.2.100, FDDR v2.0.200, and SerDes v2.0.200 cores:
  • • Reduced VCO speed-up ratio to improve PLL lock stability as operating conditions reach cold temperatures
    • Reduced dwell time at high VCO frequency for continued successful PCIe endpoint enumeration with newer generation host CPUs
• FDDR 16-bit and 8-bit width modes with ECC enabled:
  • Updated IP core top-level DQ_ECC port bit mapping to device package pin FDDR_DQ_ECC[#] for proper ECC functionality

PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

• DDR3, DDR4, and LPDDR3 fabric core updates:
  • Support for ZQCS command
  • Re-inititialization enabled to restart DDR training
  • Fast simulation training IP
  • Removal of ODT activation setting on read
• PF_XCVR CDR 3G, HD SDI: Updated transceiver register presets for "Lock to Data with 2X Gain" receiver mode to account for a wider variety of board noise environments
• IOD LANECTRL: Enhanced DRC to ensure IOD LANECTRL instances are isolated from unrelated active DLL instances
• IOD RX_CLK_ODT_EN for LVDS Failsafe: Connected RX_CLK_P to HS_IO_CLK when "Clock to Data Relationship" is configured as dynamic, centered or aligned
• Matched the encryption key of third-stage SPI-Flash binding with that of the bitstream

PolarFire SoC Standalone MSS Configurator

RT PolarFire SoC

RTPFS460ZT/ZTS/ZTL/ZTLS CG1509: Updated package pin functions

PolarFire

Introducing the following PolarFire core devices with programming support.

Introducing the following PolarFire TS Automotive TGrade2 devices.

PolarFire SoC

Introducing the following PolarFire SoC core devices with programming support.

Introducing the following PolarFire SoC TS Automotive TGrade2 devices.

Introducing the following MPFS460TS military production timing and power devices.

RT PolarFire

• RTPF500ZT/ZTS/ZTL/ZTLS: New FC1509 package
• SSN analysis for CG1509 package for RTPF500ZT/TS/TL/TLS and RTPF500T/TS/TL/TLS devices

RT PolarFire SoC

• RTPFS460ZT/ZTS/ZTL/ZTLS: New FC1509 package
• Programming and SmartDebug support for RTPFS460ZT/ZTS/ZTL/ZTLS and RTPFS160ZT/TS/TL/TLS devices
• PFSOC_SCSM: Enable SC_WAKE control by dynamic signals from fabric logic to allow temporary exit from System Controller Suspend mode to perform System Services

• Enhanced copy and paste functionality for SmartDesign HDL+ cores
• Added support to program Micron MT25QL01G SPI-Flash devices
• Enhanced the automatic programmer detection functionality
• Availability of multiple servers in LM_LICENSE_FILE environment variable
• Upgraded Synplify Pro ME tool to V-2023.09M-5 with RTG4 Dual-port Write-byte Enable, improved DSP inference report and Complete TMR report
• Upgraded the Identify tool to V-2023.09M-5 with RTG4 Pre-arm trigger and support for RT PolarFire and RT PolarFire SoC devices
• Upgraded ModelSim ME Pro and QuestaSim ME simulator tools to v2024.3
• Improved SmartTime analysis:
  • Ability to override the jitter value with clock uncertainty
  • Refined exception constraint resolution using get_clocks
  • Generated clock duty-cycle update

PolarFire, RT PolarFire, PolarFire SoC and RT PolarFire SoC Enhancements

• PF_XCVR: 64b6xb Gear Box options can be enabled or disabled independently
• Octal DDR PHY DRC limit raised to 500 Mbps
• SUBLVDS 3.3V, 2.5V GPIO: Added 3mA Output Drive setting
• PF_IO: Added option to specify Clock Edge for RX/TX/OE IOD registers
• QDR, SpaceWire: Improved I/O delays for LVDS 2.5V, HSTL 1.2V and 1.5V
• PF_IOD_GENERIC_TX: Added support to automatically repair hold violations for source-sync TX interfaces during P&R with Repair Minimum Delay Violations enabled
• Clarified I/O register usage details in Compile and Layout reports
• Board layout report: Updated Unused Condition notes
• Added calibration information in I/O Bank report
• Ability to perform Static Timing analysis at IND Temp-range for MIL devices
• Added programming support for Space Grade QSPI MRAM AS302G208-0108X0MCEY
• Simulation model enhancements:
  • LSRAM ECC error injection
  • PF_IOD_GENERIC_RX: Simulation of L0_LP_DATA and L0_LP_DATA_N at high-speed data transition
  • PF_IOD_TX_CCC: Updated 3.5 clock ratio
  • Post-layout simulation for I/O registers with SDF
• Enhanced SmartDebug:
  • New feature: MSS DDR I/O training results
  • Improvements:
    • Fabric DDR I/O Margin training results
    • XCVR persistent eye monitor
    • Signal Integrity settings persistence

RTG4, SmartFusion2 and IGLOO2 Enhancements

• RTG4FCCCECALIB: Refreshed Basic tab when PLL is in by pass mode
• SERDES cores: Transmit De-Emphasis recalculated per TX Amplitude setting
• Block design methodology: Propagate chip-level hardwired connections to the top module
• SmartFusion2, IGLOO2:
  • Added parameters to eNVM simulation model that allow the user to account for silicon delays
  • Added SVF programming
• RTG4 Report State of System Controller Suspend Mode setting in the programming bitstream at each of the following stages:
  • Generate Bitstream
  • Export Bitstream
  • Export FPExpress job
  • Run PROGRAM action
  • FPExpress when running PROGRAM action

SmartHLS

• Upgraded compilation environments:
  • Core compiler upgraded to Clang/LLVM 15.0.7
  • Software simulation compiler upgraded to GNU GCC 8.5
  • Customizable C++ standard setting through new CXX_STANDARD Makefile variable; defaults to 14 (C++14)
• Improved multiplication synthesis with new set of constraint parameters to aid in design solution exploration
• Added full support of pointer casting between primitive data types
• Soft-MiV RV32 can now run on-board using SoC Flow
• Improved HLS pipeline result report
• Enhanced debugging capabilities on HLS FIFOs in software simulation