2.2 Pin Details

The following figure illustrates the pin diagram of the IS2008S and IS2010S.

Figure 2-2. IS2008S and IS2010S Pin Diagram

The following table provides the pin description of the IS2008S and IS2010S.

Table 2-2. Pin Description
IS2008S and IS2010S Pin No	Pin Type⁽¹⁾	Pin Name	Description
1	P	VCOM	Internal biasing voltage for codec
2	I	MICN2	Mic2 mono differential analog negative input
3	I	MICP2	Mic2 mono differential analog positive input
4	I	MICN1	Mic1 mono differential analog negative input
5	I	MICP1	Mic1 mono differential analog positive input
6	P	MICBIAS	Electric microphone biasing voltage
7	P	VDD_CORE	Core 1.2V power input; connect to CLDO_O pin
8	O	P1_2	I/O pin, default pull-high input EEPROM clock SCL
9	I/O	P1_3	I/O pin, default pull-high input EEPROM data SDA
10	I	RST_N	System Reset pin, active when rising edge
11	P	VDD_IO	I/O power supply input (2.7-3.3V); connect to LDO31_VO pin
12	I/O	P0_1	I/O pin, default pull-high input⁽²⁾ FWD key when class 2 RF (default), active-low Class 1 TX control signal of external RF T/R switch, active high
13	I/O	P1_5	I/O pin, default pull high input⁽²⁾ NFC detection pin, active-low Out_Ind_0 Slide switch detector, active-low Buzzer signal output
14	I	HCI_RXD	HCI UART data input
15	O	HCI_TXD	HCI UART data output
16	P	CODEC_VO	3.1V LDO output for codec power
17	P	LDO31_VIN	3.1V LDO input; connect to SYS_PWR pin
18	P	LDO31_VO	3.1V LDO output
19	P	ADAP_IN	5V power adapter input
20	P	BAT_IN	3.3-4.2V Li-ion battery input
21	-	NC	No Connection
22	P	SAR_VDD	SAR 1.8V input; connect to BK_O pin
23	P	SYS_PWR	Power output which comes from BAT_IN or ADAP_IN
24	P	BK_VDD	1.8V buck VDD Power Input; connect to SYS_PWR pin
25	P	BK_LX	1.8V buck pin for switch
26	P	BK_O	1.8V buck feedback input
27	I	PWR	Multi function push button and power-on key
28	I	LED2	LED Driver 2
29	I	LED1	LED Driver 1
30	I/O	P0_3	I/O pin, default pull-high input⁽²⁾ REV key (default), active-low Buzzer signal output Out_Ind_1 Class 1 RX control signal of external RF T/R switch, active high
31	P	CLDO_O	1.2V core LDO output
32	P	PMIC_IN	PMU blocks power input; connect to BK_O pin
33	P	RFLDO_O	1.28V RF LDO output
34	P	VBG	Bandgap output reference for decoupling interference
35	P	ULPC_VSUS	ULPC 1.2V output power
36	I	XO_N	16 MHz crystal input negative
37	I	XO_P	16 MHz crystal input positive
38	P	VCC_RF	RF power input (1.28V) for both synthesizer and TX/RX block; connect to RFLDO_O pin
39	I/O	RTX	RF path (transmit/receive)
40	I	P0_2	I/O pin, default pull-high input⁽²⁾ Play/Pause key (default), active-low
41	I	P2_0	I/O pin, default pull-high input system configuration, H: Application L: Baseband (IBDK mode)
42	I	P2_7	I/O pin, default pull high input⁽²⁾ Volume up key (default), active-low
43	I	P0_5	I/O pin, default pull high input⁽²⁾ Volume down (default), active-low
44	P	VDD_IO	I/O power supply input (2.7-3.3V); connect to LDO31_VO pin
45	P	VDD_AO	Positive power supply dedicated to codec output amplifiers; connect to CODEC_VO pin
46	O	AOHPM	Headphone common mode output/sense input
47	O	AOHPL	Left channel, analog headphone output
48	P	VDDA	Positive power supply/reference voltage for codec; connect to CODEC_VO pin
49	P	EP	Exposed pads, used as ground (GND) pins

Note:

The conventions used in the table are indicated as follows:
- I = Input pin
- O = Output pin
- I/O = Input/Output pin
- P = Power pin
All I/O pins are configured using the IS20XXS_UI tool, a Windows^®-based utility.

The following figure illustrates the pin diagram of the IS2013S and IS2015S.

Figure 2-3. IS2013S and IS2015S Pin Diagram

The following table provides the pin description of the IS2013S/IS2015S.

Table 2-3. Pin Description
IS2013S and IS2015S Pin No	Pin Type⁽¹⁾	Pin Name	Description
1	P	VDDAO	Positive power supply dedicated to codec output amplifiers; Connect to CODEC_VO pin
2	O	AOHPM	Headphone common mode output/sense input
3	O	AOHPL	Left channel analog headphone output
4	P	VDDA	Positive power supply/reference voltage for codec; connect to CODEC_VO pin
5	P	VCOM	Internal biasing voltage for codec
6	I	MICN1	Mic1 mono differential analog negative input
7	I	MICP1	Mic1 mono differential analog positive input
8	P	MICBIAS	Electric microphone biasing voltage
9	I	AIL	Left channel single-ended analog inputs
10	P	VDD_CORE	Core 1.2V power input; connect to CLDO_O pin
11	O	P1_2	I/O pin, default pull high input EEPROM clock SCL
12	I/O	P1_3	I/O pin, default pull high input EEPROM data SDA
13	I	RST_N	System Reset pin, active when rising edge
14	P	VDD_IO	I/O power supply input (2.7-3.3V); connect to LDO31_VO pin
15	I/O	P0_1	I/O pin, default pull-high input⁽²⁾ FWD key when class 2 RF (default), active-low Class 1 TX Control signal of external RF T/R switch, active high
16	I	P2_4	I/O pin, default pull high input system configuration, L: Boot mode with P2_0 low combination
17	I/O	P0_4	I/O pin, default pull high input⁽²⁾ NFC detection pin, active-low Out_Ind_0
18	I/O	P1_5	I/O pin, default pull high input⁽²⁾ NFC detection pin, active-low Out_Ind_0 Slide switch detector, active-low Buzzer signal output
19	I	HCI_RXD	HCI UART input data
20	O	HCI_TXD	HCI UART output data
21	P	CODEC_VO	3.1V LDO output for codec power
22	P	LDO31_VIN	3.1V LDO input; connect to SYS_PWR pin
23	P	LDO31_VO	3.1V LDO output
24	P	ADAP_IN	5V power adapter input
25	P	BAT_IN	3.3 to 4.2V Li-ion battery input
26	P	SAR_VDD	SAR 1.8V input; connect to BK_O pin
27	P	SYS_PWR	Power output which come from BAT_IN or ADAP_IN
28	P	LDO18_VDD	1.8V LDO VDD Power Input; connect to SYS_PWR pin
29	P	LDO18_O	1.8V LDO output
30	I	PWR	Multi-Function Push button and power on key
31	-	NC	No Connection
32	I	LED2	LED Driver 2
33	I	LED1	LED Driver 1
34	I/O	P0_0	I/O pin, default pull-high input⁽²⁾ Slide switch detector, active-low UARTTX_IND, active-low
35	I/O	P0_3	I/O pin, default pull-high input⁽²⁾ REV key (default), active-low Buzzer signal output Out_Ind_1 Class 1 RX control signal of external RF T/R switch, active high.
36	I	EAN	Embedded ROM/External Flash enable H: Embedded; L: External Flash
37	P	CLDO_O	1.2V core LDO output
38	P	PMIC_IN	PMU blocks power input; connect to BK_O pin
39	P	RFLDO_O	1.28V RF LDO output
40	P	VBG	Bandgap output reference for decoupling interference
41	P	ULPC_VSUS	ULPC 1.2V output power
42	I	XO_N	16 MHz crystal input negative
43	I	XO_P	16 MHz crystal input positive
44	P	VCC_RF	RF power input (1.28V) for both synthesizer and TX/RX block; connect to RFLDO_O pin
45	I/O	RTX	RF path (transmit/receive)
46	I	P0_2	I/O pin, default pull-high input⁽²⁾ Play/Pause key (default), active-low
47	I	P2_0	I/O pin, default pull-high input system configuration, H: Application L: Baseband (IBDK mode)
48	I	P2_7	I/O pin, default pull-high input⁽²⁾ Volume up key (default), active-low
49	I	P3_0	I/O pin, default pull-high input⁽²⁾ Line-in detector (default), active-low
50	I	P0_5	I/O pin, default pull-high input⁽²⁾ Volume down (default), active-low
51	P	VDD_IO	I/O power supply input (2.7-3.3V); connect to LDO31_VO pin
52	P	AVDD_CDA	Supply voltage of audio amplifier
53	P	VBP_CDA	Reference voltage output.
54	O	HPON_CDA	Negative BTL output of channel-1
55	O	HPOP_CDA	Positive BTL output of channel-1
56	P	PVDD_CDA	Supply voltage of power stage ch-1
57	P	EP	Exposed pads, used as ground (GND) pins

Note:

The conventions used in the table are indicated as follows:
- I = Input pin
- O = Output pin
- I/O = Input/Output pin
- P = Power pin
All I/O pins are configured using the UI tool, a Windows-based utility.

IS2008S/IS2010S/IS2013S/IS2015S

2.2 Pin Details