1.8.2.3 Pin Description

The device features several PIO controllers that multiplex the I/O lines of the peripheral set. The following Pin Description table defines how the I/O lines are multiplexed on the different PIO controllers. The "Reset State" column shows whether the PIO line resets in I/O mode or in Peripheral mode. If I/O is shown, the PIO line resets with the characteristics (input, output, pull–up or pull–down) indicated in this same column, so that the device is configured in a known state as soon as the reset is released. As a result, PIO_CFGR.FUNC resets to ‘0’. If a signal name is shown in the “Reset State” column, the PIO line is assigned to this function and PIO_CFGR.FUNC is not set to ‘0’. That is the case for pins controlling memories, in particular address lines, which require the pin to be driven as soon as the reset is released.

Table 1-4. Pin Description(1)

228-pin

BGA

256-pin

BGA

Power Rail

I/O

Type(2)

PrimaryAlternatePIO PeripheralReset State(4)
SignalDirSignalDirFuncSignalDir

I/O

Set(3)

P2P4VDDIOP0GPIO PA0I/OAFLEXCOM0_IO0I/O1PIO, I, PU, ST
BFLEXCOM5_IO4O1
CFLEXCOM4_IO4O2
M3N4VDDIOP0GPIOPA1I/OAFLEXCOM0_IO1I/O1PIO, I, PU, ST
BFLEXCOM4_IO5O1
P1U2VDDIOP0GPIOPA2I/OWKUP1AFLEXCOM0_IO4O1PIO, I, PU, ST
BSDMMC1_DAT1I/O1
CE0_TX0O2
L3K7VDDIOP0GPIOPA3I/OAFLEXCOM0_IO3I/O1PIO, I, PU, ST
BSDMMC1_DAT2I/O1
CE0_TX1O2
N1T2VDDIOP0GPIOPA4I/OAFLEXCOM0_IO2I/O1PIO, I, PU, ST
BSDMMC1_DAT3I/O1
CE0_TXERO2
L4M5VDDIOP0GPIOPA5I/OAFLEXCOM1_IO0I/O1PIO, I, PU, ST
BCANTX1O1
M2R2VDDIOP0GPIOPA6I/OAFLEXCOM1_IO1I/O1PIO, I, PU, ST
BCANRX1I1
K6L5VDDIOP0GPIOPA7I/OAFLEXCOM2_IO0I/O1PIO, I, PU, ST
BFLEXCOM4_IO4O1
CFLEXCOM5_IO4O2
M1T1VDDIOP0GPIOPA8I/OAFLEXCOM2_IO1I/O1PIO, I, PU, ST
BFLEXCOM5_IO3I/O1,2
CFLEXCOM4_IO5O2
G8R3VDDIOP0GPIOPA9I/OWKUP2ADRXDI1PIO, I, PU, ST
BCANRX0I1
L2P2VDDIOP0GPIOPA10I/OWKUP3ADTXDO1PIO, I, PU, ST
BCANTX0O1
H7P3VDDIOP0GPIOPA11I/OAFLEXCOM4_IO1I/O1,2PIO, I, PU, ST
BSDMMC1_DAT0I/O1
L1R1VDDIOP0GPIOPA12I/OAFLEXCOM4_IO0I/O1,2PIO, I, PU, ST
BSDMMC1_CMDI/O1
J6M4VDDIOP0GPIOPA13I/OAFLEXCOM4_IO2I/O1,2PIO, I, PU, ST
BSDMMC1_CKI/O1
K1P1VDDIOP0GPIOPA14I/OAFLEXCOM4_IO3I/O1,2PIO, I, PU, ST
H6N3VDDIOP0GPIOPA15I/OASDMMC0_DAT0I/O1PIO, I, PU, ST
K2N1VDDIOP0GPIOPA16I/OASDMMC0_CMDI/O1PIO, I, PU, ST
J3M3VDDIOP0GPIOPA17I/OASDMMC0_CKI/O1PIO, I, PU, ST
J1M1VDDIOP0GPIOPA18I/OASDMMC0_DAT1I/O1PIO, I, PU, ST
J5L4VDDIOP0GPIOPA19I/OASDMMC0_DAT2I/O1PIO, I, PU, ST
J2L1VDDIOP0GPIOPA20I/OASDMMC0_DAT3I/O1PIO, I, PU, ST
G6K3VDDIOP0GPIOPA21I/OATIOA0I/O1PIO, I, PU, ST
BFLEXCOM5_IO1I/O1,2
G1J1VDDIOP0GPIOPA22I/OATIOA1I/O1PIO, I, PU, ST
BFLEXCOM5_IO0I/O1,2
J4J3VDDIOP0GPIOPA23I/OATIOA2I/O1PIO, I, PU, ST
BFLEXCOM5_IO2I/O1,2
F8L2VDDIOP0GPIOPA24I/OATCLK0I1PIO, I, PU, ST
BTKI/O1
CCLASSD_L0O1
H1K1VDDIOP0GPIOPA25I/OATCLK1I1PIO, I, PU, ST
BTFI/O1
CCLASSD_L1O1
F7L3VDDIOP0GPIOPA26I/OATCLK2I1PIO, I, PU, ST
BTDO1
CCLASSD_L2O1
H2K2VDDIOP0GPIOPA27I/OATIOB0I/O1PIO, I, PU, ST
BRDI1
CCLASSD_L3O1
F1G1VDDIOP0GPIOPA28I/OWKUP4ATIOB1I/O1PIO, I, PU, ST
BRKI/O1
H3H3VDDIOP0GPIOPA29I/OATIOB2I/O1PIO, I, PU, ST
BRFI/O1
CFLEXCOM2_IO7I1
G2H1VDDIOP0GPIOPA30I/OAFLEXCOM6_IO0I/O1PIO, I, PU, ST
BFLEXCOM5_IO6O1,2
CE0_MDCO2
H4J4VDDIOP0GPIOPA31I/OAFLEXCOM6_IO1I/O1PIO, I, PU, ST
BFLEXCOM5_IO5O1,2
CE0_TXENO2
F4F3VDDANAGPIOPB0I/OWKUP5AE0_RX0I1,2PIO, I, PU, ST
BFLEXCOM2_IO4O1
C1E1VDDANAGPIOPB1I/OAE0_RX1I1,2PIO, I, PU, ST
BFLEXCOM2_IO3I/O1
D3F5VDDANAGPIOPB2I/OAE0_RXERI1,2PIO, I, PU, ST
BFLEXCOM2_IO2I/O1
D1F1VDDANAGPIOPB3I/OWKUP6AE0_RXDVI1,2PIO, I, PU, ST
BFLEXCOM4_IO6O1,2
E3G5VDDANAGPIOPB4I/OAE0_TXCKI/O1,2PIO, I, PU, ST
BFLEXCOM8_IO0I/O1
E1G2VDDANAGPIOPB5I/OAE0_MDIOI/O1,2PIO, I, PU, ST
BFLEXCOM8_IO1I/O1
D2C1VDDANAGPIOPB6I/OAD7AE0_MDCO1PIO, I, PU, ST
BFLEXCOM0_IO7I1
A5D3VDDANAGPIOPB7I/OAD8AE0_TXENO1PIO, I, PU, ST
E6E4VDDANAGPIOPB8I/OAD9AE0_TXERO1PIO, I, PU, ST
A2B1VDDANAGPIOPB9I/OAD10AE0_TX0O1PIO, I, PU, ST
BPCK1O1
A3B2VDDANAGPIOPB10I/OAD11AE0_TX1O1PIO, I, PU, ST
BPCK0O1
D6E5VDDANAGPIOPB11I/OAD0AE0_TX2O1,2PIO, I, PU, ST
BPWM0O2
C2C2VDDANAGPIOPB12I/OAD1AE0_TX3O1,2PIO, I, PU, ST
BPWM1O2
A4E3VDDANAGPIOPB13I/OAD2AE0_RX2I1,2PIO, I, PU, ST
BPWM2O2
F2D2VDDANAGPIOPB14I/OAD3AE0_RX3I1,2PIO, I, PU, ST
BPWM3O2
B5D5VDDANAGPIOPB15I/OAD4AE0_RXCKI1,2PIO, I, PU, ST
B3F4VDDANAGPIOPB16I/OAD5AE0_CRSI1,2PIO, I, PU, ST
B1D1VDDANAGPIOPB17I/OAD6AE0_COLI1,2PIO, I, PU, ST
E4H5VDDANAGPIOPB18I/OWKUP7AIRQI1PIO, I, PU, ST
BADTRGNone1
C6C6VDDIOQSPIGPIOPB19I/OAQSCKO1PIO, I, PU, ST
BI2SMCC_CKI/O1
CFLEXCOM11_IO0I/O1
A6A2VDDIOQSPIGPIOPB20I/OAQCSO1PIO, I, PU, ST
BI2SMCC_WSI/O1
CFLEXCOM11_IO1I/O1
A7A3VDDIOQSPIGPIOPB21I/OAQIO0I/O1PIO, I, PU, ST
BI2SMCC_DIN0I1
CFLEXCOM12_IO0I/O1
B7D6VDDIOQSPIGPIOPB22I/OAQIO1I/O1PIO, I, PU, ST
BI2SMCC_DOUT0O1
CFLEXCOM12_IO1I/O1
B6B6VDDIOQSPIGPIOPB23I/OAQIO2I/O1PIO, I, PU, ST
BI2SMCC_MCKO1
A8E6VDDIOQSPIGPIOPB24I/OAQIO3I/O1PIO, I, PU, ST
E2J2VDDIOP0GPIOPB25I/OWKUP8ANRST_OUTO1NRST_OUT, O, PD
BNTRSTI1
M4N6VDDIOP1GPIOPC0I/OALCDDAT0O1PIO, I, PU, ST
BISI_D0I1
CFLEXCOM7_IO0I/O1
P4R4VDDIOP1GPIOPC1I/OALCDDAT1O1PIO, I, PU, ST
BISI_D1I1
CFLEXCOM7_IO1I/O1
N5L7VDDIOP1GPIOPC2I/OALCDDAT2O1PIO, I, PU, ST
BISI_D2I1
CTIOA3I/O1
P5T4VDDIOP1GPIOPC3I/OALCDDAT3O1PIO, I, PU, ST
BISI_D3I1
CTIOB3I/O1
L5L8VDDIOP1GPIOPC4I/OALCDDAT4O1PIO, I, PU, ST
BISI_D4I1
CTCLK3I1
R4R5VDDIOP1GPIOPC5I/OALCDDAT5O1PIO, I, PU, ST
BISI_D5I1
CTIOA4I/O1
M6N7VDDIOP1GPIOPC6I/OALCDDAT6O1PIO, I, PU, ST
BISI_D6I1
CTIOB4I/O1
T3U5VDDIOP1GPIOPC7I/OALCDDAT7O1PIO, I, PU, ST
BISI_D7I1
CTCLK4I1
N8N8VDDIOP1GPIOPC8I/OALCDDAT8O1PIO, I, PU, ST
BISI_D8I1
CFLEXCOM9_IO0I/O1
T4T5VDDIOP1GPIOPC9I/OALCDDAT9O1PIO, I, PU, ST
BISI_D9I1
CFLEXCOM9_IO1I/O1
P6U6VDDIOP1GPIOPC10I/OALCDDAT10O1PIO, I, PU, ST
BISI_D10I1
CPWM0O3
N6P7VDDIOP1GPIOPC11I/OALCDDAT11O1PIO, I, PU, ST
BISI_D11I1
CPWM1O3
R5T6VDDIOP1GPIOPC12I/OALCDDAT12O1PIO, I, PU, ST
BISI_PCKI1
CTIOA5I/O1
L7L9VDDIOP1GPIOPC13I/OALCDDAT13O1PIO, I, PU, ST
BISI_VSYNCI1
CTIOB5I/O1
T5R6VDDIOP1GPIOPC14I/OALCDDAT14O1PIO, I, PU, ST
BISI_HSYNCI1
CTCLK5I1
J7L10VDDIOP1GPIOPC15I/OALCDDAT15O1PIO, I, PU, ST
BISI_MCKO1
CPCK0O2
R6T7VDDIOP1GPIOPC16I/OALCDDAT16O1,2PIO, I, PU, ST
BE1_RXERI1
CFLEXCOM10_IO0I/O1
K8R7VDDIOP1GPIOPC17I/OALCDDAT17O1,2PIO, I, PU, ST
BFLEXCOM1_IO7I1
CFLEXCOM10_IO1I/O1
T6U7VDDIOP1GPIOPC18I/OALCDDAT18O1,2PIO, I, PU, ST
BE1_TX0O1
CPWM0O1
L8L11VDDIOP1GPIOPC19I/OALCDDAT19O1,2PIO, I, PU, ST
BE1_TX1O1
CPWM1O1
P8T8VDDIOP1GPIOPC20I/OALCDDAT20O1,2PIO, I, PU, ST
BE1_RX0I1
CPWM2O1
M8N11VDDIOP1GPIOPC21I/OALCDDAT21O1,2PIO, I, PU, ST
BE1_RX1I1
CPWM3O1
R7U8VDDIOP1GPIOPC22I/OALCDDAT22O1,2PIO, I, PU, ST
BFLEXCOM3_IO0I/O1
K9N10VDDIOP1GPIOPC23I/OALCDDAT23O1,2PIO, I, PU, ST
BFLEXCOM3_IO1I/O1
R8R8VDDIOP1GPIOPC24I/OWKUP9ALCDDISPO1,2PIO, I, PU, ST
BFLEXCOM3_IO4O1
L9P9VDDIOP1GPIOPC25I/OWKUP10BFLEXCOM3_IO3I/O1PIO, I, PU, ST
T8R9VDDIOP1GPIOPC26I/OALCDPWMO1,2PIO, I, PU, ST
BFLEXCOM3_IO2I/O1
M9N9VDDIOP1GPIOPC27I/OALCDVSYNCO1,2PIO, I, PU, ST
BE1_TXENO1
CFLEXCOM1_IO4O1
N9N12VDDIOP1GPIOPC28I/OALCDHSYNCO1,2PIO, I, PU, ST
BE1_CRSDVI1
CFLEXCOM1_IO3I/O1
L10P11VDDIOP1GPIOPC29I/OALCDDENO1,2PIO, I, PU, ST
BE1_TXCKI/O1
CFLEXCOM1_IO2I/O1
T7P10VDDIOP1GPIOPC30I/OALCDPCKO1,2PIO, I, PU, ST
BE1_MDCO1
CFLEXCOM3_IO7I1
M13N13VDDIOP1GPIOPC31I/OWKUP11AFIQI1PIO, I, PU, ST
BE1_MDIOI/O1
CPCK1O2
R14P16VDDNFGPIOPD0I/OANANDOEO1PIO, I, PU
T15P15VDDNFGPIOPD1I/OANANDWEO1PIO, I, PU
P15N15VDDNFGPIOPD2I/OAA21/NANDALEO1A21,O, PD
N14N14VDDNFGPIOPD3I/OAA22/NANDCLEO1A22,O, PD
R16M15VDDNFGPIOPD4I/OANCS3O1PIO, I, PU
N11L15VDDNFGPIOPD5I/OANWAITI1PIO, I, PU
K16K15VDDNFGPIOPD6I/OAD16I/O1PIO, I, PU
J12J13VDDNFGPIOPD7I/OAD17I/O1PIO, I, PU
K15K16VDDNFGPIOPD8I/OAD18I/O1PIO, I, PU
J10J14VDDNFGPIOPD9I/OAD19I/O1PIO, I, PU
L16K17VDDNFGPIOPD10I/OAD20I/O1PIO, I, PU
K11K14VDDNFGPIOPD11I/OAD21I/O1PIO, I, PU
L15L17VDDNFGPIOPD12I/OAD22I/O1PIO, I, PU
J15K13VDDNFGPIOPD13I/OAD23I/O1PIO, I, PU
L12L13VDDNFGPIOPD14I/OAD24I/O1PIO, I, PU
M16L16VDDNFGPIOPD15I/OAD25I/O1A20, O, PD
BA20O1
M14L14VDDNFGPIOPD16I/OAD26I/O1A23, O, PD
BA23O1
N16M17VDDNFGPIOPD17I/OWKUP12AD27I/O1A24, O, PD
BA24O1
L13M13VDDNFGPIOPD18I/OWKUP13AD28I/O1A25, O, PD
BA25O1
P16N17VDDNFGPIOPD19I/OAD29I/O1PIO, I, PU
BNCS2O1
M11M14VDDNFGPIOPD20I/OAD30I/O1PIO, I, PU
BNCS4O1
M15N16VDDNFGPIOPD21I/OAD31I/O1PIO, I, PU
BNCS5O1
C10C12VDDIOMPowerVDDIOM
C13E8VDDIOMPowerVDDIOM
G14E13VDDIOMPowerVDDIOM
A1H13GNDGroundGND
T1H16GNDGroundGND
N2J7GNDGroundGND
G5K5GNDGroundGND
K14R15VDDNF PowerVDDNF
K5K11GNDGroundGND
E7M2GNDGroundGND
M7P6GNDGroundGND
G3G3VDDIOP0PowerVDDIOP0
K3K4VDDIOP0PowerVDDIOP0
H8P17GNDGroundGND
J8R16GNDGroundGND
N3P8VDDIOP1PowerVDDIOP1
H9T3GNDGroundGND
P7R10VDDBUPowerVDDBU
E10T9GNDGroundGND
C4C3VDDANAPowerVDDANA
B4B3GNDANAGroundGNDANA
G12T13GNDGroundGND
K12T17GNDGroundGND
P10T11VDDIN33PowerVDDOUT25
L11R12VDDIN33PowerVDDIN33
R13U11GNDIN33GroundGNDIN33
F6J11VDDCOREPowerVDDCORE
L6N2VDDCOREPowerVDDCORE
F11P5VDDCOREPowerVDDCORE
B13U1GNDGroundGND
N15U9GNDGroundGND
A16U13GNDGroundGND
C7C5VDDQSPIPowerVDDQSPI
T16U17GNDGroundGND
P13R13VDDIN33PowerVDDIN33
M10R14GNDIN33GroundGNDIN33
H16E17VDDIOMDDRIOD0O, PD
H10F16VDDIOMDDRIOD1O, PD
H15F17VDDIOMDDRIOD2O, PD
H11G15VDDIOMDDRIOD3O, PD
J14G16VDDIOMDDRIOD4O, PD
J11H14VDDIOMDDRIOD5O, PD
J16H15VDDIOMDDRIOD6O, PD
J13J15VDDIOMDDRIOD7O, PD
G9D7VDDIOMDDRIOD8O, PD
D8B7VDDIOMDDRIOD9O, PD
F9C7VDDIOMDDRIOD10O, PD
A9A7VDDIOMDDRIOD11O, PD
F10D9VDDIOMDDRIOD12O, PD
B9B9VDDIOMDDRIOD13O, PD
D11D10VDDIOMDDRIOD14O, PD
C9C9VDDIOMDDRIOD15O, PD
B10B10VDDIOMDDRIOA0NBS0O, PD
G16J16VDDIOMDDRIOA1NBS2/DQM2/NWR2O, PD
A13B12VDDIOMDDRIOA2O, PD
D15D12VDDIOMDDRIOA3O, PD
B12B11VDDIOMDDRIOA4O, PD
E11E12VDDIOMDDRIOA5O, PD
A12A10VDDIOMDDRIOA6O, PD
B16C16VDDIOMDDRIOA7O, PD
F16C17VDDIOMDDRIOA8O, PD
D14E10VDDIOMDDRIOA9O, PD
C11E9VDDIOMDDRIOA10O, PD
E13C13VDDIOMDDRIOA11O, PD
A11C10VDDIOMDDRIOA12O, PD
B11A9VDDIOMDDRIOA13O, PD
C15D11VDDIOMDDRIOA14O, PD
G15D17VDDIOMDDRIOA15O, PD
E14C15VDDIOMDDRIOA16BA0O, PD
F14F15VDDIOMDDRIOA17BA1O, PD
C16B17VDDIOMDDRIOA18BA2O, PD
H14F13VDDIOMDDRIOA19O, PD
F15E16VDDIOMDDRIONCS0O, PU
E16D16VDDIOMDDRIONCS1SDCSO, PU
F12E15VDDIOMDDRIONRDO, PU
E8D8VDDIOMDDRIONWR0NWEO, PU
A10A5VDDIOMDDRIONWR1NBS1O, PU
L14M16VDDIOMDDRIONWR3NBS3/DQM3O, PU
A15A15VDDIOMDDRIOSDCKO, PD
B14A14VDDIOMDDRIOSDCKNO, PU
F13F14VDDIOMDDRIOSDCKEO, PU
E15D15VDDIOMDDRIORASO, PU
C12B14VDDIOMDDRIOCASO, PU
D16C14VDDIOMDDRIOSDWEO, PU
D12E11VDDIOMDDRIOSDA10O, PU
G11G14VDDIOMDDRIODQM0O, PU
C8A6VDDIOMDDRIODQM1O, PU
H12H17VDDIOMDDRIODQS0O, PD
H13J17VDDIOMDDRIONDQS0O, PU
D9B8VDDIOMDDRIODQS1O, PD
E9A8VDDIOMDDRIONDQS1O, PU
B8C8VDDIOMDDRANADDR_CALI/OI
A14A12VDDIOMDDRANADDR_VREFI/OI
D5B4VDDANAGPIOADVREFPII
C5C4VDDANAGPIOADVREFNII
P11R17VDDIN33USBHSHHSRTUNEI/OI
T12U14VDDIN33USBHSHHSDPAI/ODHSDPO, PD
R12T14VDDIN33USBHSHHSDMAI/ODHSDMO, PD
T13U15VDDIN33USBHSHHSDPBI/OO, PD
T14T15VDDIN33USBHSHHSDMBI/OO, PD
P12U16VDDIN33USBHSHHSDPCI/OO, PD
N12T16VDDIN33USBHSHHSDMCI/OO, PD
T11R11VDDBUSYSCWKUP0II, ST
R11P12VDDBUSYSCSHDNOO, PD
P9P14VDDBUSYSCJTAGSELII, PD
J9P13VDDBUSYSCTSTI, PD, ST
R3U3VDDIOP0RSTJTAGTCKII, ST
F3H2VDDIOP0RSTJTAGTDIII, ST
H5J5VDDIOP0RSTJTAGTDOOO
F5H4VDDIOP0RSTJTAGTMSII, ST
T2U4VDDIOP0RSTJTAGRTCKOO
R1N5VDDIOP0RSTJTAGNRSTII, PU, ST
T9T10VDDBUCLOCKXIN32II
R9U10VDDBUCLOCKXOUT32I/OO
R10U12VDDIN33CLOCKXINII
T10T12VDDIN33CLOCKXOUTI/OO
E7VDDCOREPowerVDDCORE
G9VDDCOREPowerVDDCORE
G11VDDCOREPowerVDDCORE
G13VDDCOREPowerVDDCORE
H7VDDCOREPowerVDDCORE
H11VDDCOREPowerVDDCORE
E2VDDCOREPowerVDDCORE
A1GNDGroundGND
A4GNDGroundGND
A11GNDGroundGND
A13GNDGroundGND
A16GNDGroundGND
A17GNDGroundGND
B5GNDGroundGND
B13GNDGroundGND
B15GNDGroundGND
B16GNDGroundGND
C11GNDGroundGND
D4GNDGroundGND
D13GNDGroundGND
D14GNDGroundGND
E14GNDGroundGND
F2GNDGroundGND
G4GNDGroundGND
G7GNDGroundGND
G8GNDGroundGND
G10GNDGroundGND
G17GNDGroundGND
  1. When using an I/O line with the Analog–to–Digital Converter (ADC), the PIO line configuration (pull–up, pull–down) programmed before assigning this line to the ADC peripheral is not modified by this peripheral.
  2. Refer to the Electrical Characteristics section for further details.
  3. I/Os for each peripheral are grouped into I/O sets, listed in the column "I/O Set". For all peripherals, use I/Os that belong to the same I/O set. Timings can be unpredictable when I/Os from different I/O sets are mixed.

  4. Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull–up; PD = Pull–down; HiZ = High impedance; ST = Schmitt Trigger