43.7.2 ADCON1
| Name: | ADCON1 |
| Address: | 0x3F4 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PPOL | IPEN | GPOL | DSEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – PPOL Precharge Polarity
| Value | Name | Description |
|---|---|---|
| x | ADPRE = 0 |
Bit has no effect |
| 1 | ADPRE > 0 |
External analog I/O pin is connected to VDD Internal AD sampling capacitor (CHOLD) is connected to VSS |
| 0 | ADPRE > 0 |
External analog I/O pin is connected to VSS Internal AD sampling capacitor (CHOLD) is connected to VDD |
Bit 6 – IPEN A/D Inverted Precharge Enable
| Value | Name | Description |
|---|---|---|
| x | DSEN = 0 |
Bit has no effect |
| 1 | DSEN = 1 |
The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle |
| 0 | DSEN = 1 |
Both Conversion cycles use the precharge and guards specified by PPOL and GPOL |
Bit 5 – GPOL Guard Ring Polarity Selection
| Value | Description |
|---|---|
| 1 | ADC guard Ring outputs start as digital high during Precharge stage |
| 0 | ADC guard Ring outputs start as digital low during Precharge stage |
Bit 0 – DSEN Double-Sample Enable
| Value | Description |
|---|---|
| 1 | Two conversions are processed as a pair. The selected computation is performed after every second conversion. |
| 0 | Selected computation is performed after every conversion |