43.7.6 ADCLK

ADC Clock divider Register

Note: ADC Clock divider is only available if F_OSC is selected as the ADC clock source (CS = 0).

Name:	ADCLK
Address:	0x3FA


Bit	7	6	5	4	3	2	1	0
			CS[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 5:0 – CS[5:0] ADC Clock divider Select

Value	Description
n	ADC Clock frequency = F_OSC/(2*(n+1))

ADC Clock divider is only available if FOSC is selected as the ADC clock source (CSADC Clock Selection = 0).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.