3.2.6.4 PIOD Bank

The PIOD bank is mainly used for the WILC3000 radio module and Ethernet 10/100, over power rails VDDSDMMC2 and VDDIOP1, respectively.

The following schematic shows the PIOD bank distribution.

Figure 3-18. SAMA7G5 PIOD Bank Distribution

The following table describes each PIOD bank function.

Table 3-8. SAMA7G5 PIOs Pin Assignment and Signal Description
PIOPower RailFunctionSignal Description
PD0VDDIN33AD14mikroBUS 1 analog input
PD1VDDIN33AD15mikroBUS 2 analog input
PD2VDDSDMMC2SDMMC2_RSTNWILC3000 SDIO reset line
PD3VDDSDMMC2SDMMC2_CMDWILC3000 SDIO command line
PD4VDDSDMMC2SDMMC2_CKWILC3000 SDIO clock line
PD5VDDSDMMC2SDMMC2_DAT0WILC3000 SDIO data line 0
PD6VDDSDMMC2SDMMC2_DAT1WILC3000 SDIO data line 1
PD7VDDSDMMC2SDMMC2_DAT2WILC3000 SDIO data line 2
PD8VDDSDMMC2SDMMC2_DAT3WILC3000 SDIO data line 3
PD9VDDIOP1PD9MCP16502 interrupt
PD10VDDIOP1PD10WILC3000 interrupt
PD11VDDIOP1PD11Power detect USB port A
PD12VDDIOP1CANTX0CAN transmit line 0
PD13VDDIOP1CANRX0CAN receive line 0
PD14VDDIOP1CANTX1CAN transmit line 1
PD15VDDIOP1CANRX1CAN receive line 1
PD16VDDIOP1FLEXCOM3_IO0Debug UART TX line
PD17VDDIOP1FLEXCOM3_IO1Debug UART RX line
PD18VDDIOP1FLEXCOM4_IO0mikroBUS 1 UART TX line
PD19VDDIOP1FLEXCOM4_IO1mikroBUS 1 UART RX line
PD20VDDIOP1PWMH3LED blue control or mikroBUS 2 PWM control
PD21VDDIOP1G1_TXEN/PD21Transmit enable or RPi connector GPIO
PD22VDDIOP1G1_TX0/PDMC0_CLKTransmit data line 0 or PDM clock line
PD23VDDIOP1G1_TX1/PDMC0_DS0Transmit data line 1 or PDM data line 0
PD24VDDIOP1G1_CRSDV/PDMC0_DS1Carrier sense and data valid or PDM data line 1
PD25VDDIOP1G1_RX0/PD25Receive data line 0 or RPi connector GPIO
PD26VDDIOP1G1_RX1/PD26Receive data line 1 or RPi connector GPIO
PD27VDDIOP1G1_RXER/PD27Receive Error or RPi connector GPIO
PD28VDDIOP1G1_MDC/PWML3Management data clock or RPi connector GPIO
PD29VDDIOP1G1_MDIO/PD29Management data input/output or RPi connector GPIO
PD30VDDIOP1G1_TXCK/PD30Transmit clock or RPi connector GPIO
PD31VDDIOP1PD31RPi connector GPIO