3.2.6.1 PIOA Bank

The PIOA bank is mainly used for the e.MMC memory and Gigabit Ethernet over power rails VDDSDMMC0 and VDDIOP0, respectively.

The following schematic shows the PIOA bank distribution.

Figure 3-15. SAMA7G5 PIOA Bank Distribution

The following table describes each PIOA bank function.

Table 3-5. SAMA7G5 PIOs Pin Assignment and Signal Description
PIOPower RailFunctionSignal Description
PA0VDDSDMMC0SDMMC0_CKe.MMC clock Signal
PA1VDDSDMMC0SDMMC0_CMDe.MMC command line
PA2VDDSDMMC0SDMMC0_RSTNe.MMC reset signal
PA3VDDSDMMC0SDMMC0_DAT0e.MMC data line 0
PA4VDDSDMMC0SDMMC0_DAT1e.MMC data line 1
PA5VDDSDMMC0SDMMC0_DAT2e.MMC data line 2
PA6VDDSDMMC0SDMMC0_DAT3e.MMC data line 3
PA7VDDSDMMC0SDMMC0_DAT4e.MMC data line 4
PA8VDDSDMMC0SDMMC0_DAT5e.MMC data line 5
PA9VDDSDMMC0SDMMC0_DAT6e.MMC data line 6
PA10VDDSDMMC0SDMMC0_DAT7e.MMC data line 7
PA11VDDSDMMC0SDMMC0_DSe.MMC data strobe
PA12VDDIOP0PA12User button
PA13VDDIOP0PWMH2Green LED control or mikroBUS 1 PWM control
PA14VDDIOP0SDMMC0_CDe.MMC card detect
PA15VDDIOP0G0_TXENTransmit enable
PA16VDDIOP0G0_TX0Transmit data line 0
PA17VDDIOP0G0_TX1Transmit data line 1
PA18VDDIOP0G0_RXCTLReceive data valid and receive error
PA19VDDIOP0G0_RX0Receive data line 0
PA20VDDIOP0G0_RX1Receive data line 1
PA21VDDIOP0PA21Ethernet 1 interrupt (10/100 Ethernet)
PA22VDDIOP0G0_MDCManagement data clock
PA23VDDIOP0G0_MDIOManagement data input/output
PA24VDDIOP0G0_TXCKTransmit clock
PA25VDDIOP0G0_125CK125 MHz clock
PA26VDDIOP0G0_TX2Transmit data line 2
PA27VDDIOP0G0_TX3Transmit data line 3
PA28VDDIOP0G0_RX2Receive data line 2
PA29VDDIOP0G0_RX3Receive data line 3
PA30VDDIOP0G0_RXCKReceive clock
PA31VDDIOP0PA31Ethernet 0 interrupt (Gigabit Ethernet)