25.3.4 Operation Considerations

Take some considerations when using the TCF.
  • When writing to one of the CTRLA, CTRLC, CTRLD, CNT, or CMP registers, it is not allowed to write a new value before the register content has been transferred to its destination. Each of the mentioned registers has an individual synchronization, which means that, e.g., writing to CTRLA does not disturb a CTRLC write in progress. Use the TCFn.STATUS to detect that a transfer to the destination register is finished.
  • The CNT, CMP, and CTRLA/C/D registers might get corrupted when switching clock sources. A safe procedure for switching clock source is:
    • Disable the TCF
    • Disable the TCF interrupts by clearing OVF and CMPn bit fields in the TCFn.INTCTRL register
    • Select the clock source by setting the CLKSEL bit field in the TCFn.CTRLB register as appropriate
    • Write new values to TCFn.CNT, TCFn.CMP and TCFn.CTRLA/C/D registers
    • Wait for BUSY flags to be cleared
    • Clear the TCF Interrupt flags
    • Optional: Enable interrupts
    • Enable the TCF
  • The CNT and CTRLA/C/D registers are updated directly after a write operation, while CMP is updated at an overflow condition. If immediate synchronization of the CMP register is needed, this may be initiated through the UPDATE command using the CMD bit field in the CTRLD register.
  • When entering Standby sleep mode after having written to CNT, CMP, or CTRLA/C/D, EVCTRL, the clock request is held until the registers are updated.
  • When the TCF operating is in Standby sleep mode and the interrupt condition is met, the wake-up process starts on the following cycle of the TCF clock, meaning that the timer is always advanced by at least one before the processor can read the counter value.
  • The synchronization of the TCF interrupt flags takes three peripheral cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the interrupt flag to be set.
  • Reading the CNT register shortly after wake-up from Standby sleep mode may give an incorrect result. Since CNT is clocked on the asynchronous domain, reading the CNT will be done through a register synchronized to the internal I/O clock domain. Synchronization happens whenever there is a new counter value and no ongoing write synchronization. When waking up from Standby sleep mode, the CNT will read as the previous value (as before entering sleep) until the next rising edge of the asynchronous clock. The phase of the clock after waking up from Standby sleep mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading CNT is thus as follows:
    • Wait for the Counter Synchronization Busy (CNTBUSY) bit in the TCFn.STATUS register to be cleared
    • Read the TCFn.CNT register
  • The Waveform Output (WOn) pin is changed on the timer clock and is not synchronized to the processor clock.