23.3.4.4.4 Dual-Slope PWM

For the Dual-Slope PWM generation, the period (T) is controlled by TCEn.PER, while the values of TCEn.CMPn control the duty cycle of the WG output.

The figure below shows how, for Dual-Slope PWM, the counter repeatedly counts from BOTTOM to TOP and then from TOP to BOTTOM. The waveform generator output is set at BOTTOM, cleared on compare match when up-counting, and set on compare match when down-counting.

CMPn = BOTTOM produces a static low signal on WOn, while CMPn = TOP produces a static high signal on WOn.

Figure 23-12. Dual-Slope Pulse-Width Modulation

The Period (TCEn.PER) register defines the PWM resolution. The minimum resolution is two bits (TCEn.PER = 0x0003), and the maximum is 16 bits (TCEn.PER = MAX).

The following equation calculates the exact resolution in bits for Dual-Slope PWM (R_{PWM_DS}):

R_{PWM_DS} = \frac{\log (PER + 1)}{\log (2)}

The PWM frequency depends on the period setting in the TCEn.PER register, the peripheral clock frequency (f_{CLK_PER}), and the prescaler divider selected in the CLKSEL bit field in the TCEn.CTRLA register. It is calculated by the following equation:

f_{PWM_DS} = \frac{f_{CLK_PER}}{2 N \times PER}

N represents the prescaler divider used.

Using Dual-Slope PWM results in approximately half the maximum operation frequency compared to Single-Slope PWM operation due to twice the number of timer increments per period.