23.3.4.4 Compare Channel

Each Compare Channel n continuously compares the Counter (TCEn.CNT) register with the Compare n (TCEn.CMPn) register. If TCEn.CNT equals TCEn.CMPn, the Comparator n signals a match. The match will set the Compare Channel’s interrupt flag at the next timer clock cycle, generating the optional interrupt.

The Compare n Buffer (TCEn.CMPnBUF) register provides a double-buffer capability equivalent to that for the period buffer. The double-buffering synchronizes the update of the TCEn.CMPn register with the buffer value to either the TOP or BOTTOM of the counting sequence, according to the UPDATE condition. The synchronization prevents the occurrence of odd-length, non-symmetrical pulses for glitch-free output.

The value in CMPnBUF is moved to CMPn at the UPDATE condition and compared to the Counter (TCEn.CNT) register from the next count. If the CMPnBUF contains the same value as TCEn.CNT, a match event will not occur.