7.3 Transceiver Performance Characteristics

The following data shows the WLR089U0 performance as a combined system under the following conditions:
  • Modulation = LoRa
  • VCC = 3.3 VDC
  • Temperature = 25°C
  • FRF_XTA = 32.000000 MHz +/- 1 ppm (TCXO)
  • DFLL = 48 MHz
  • BW = 125 kHz
  • SF = 12
  • EC = 4/6
  • PER = 1%
  • CRC = Enabled
  • Payload = 64 bytes
  • Preamble = 12 symbols
  • Matched Impedance

Estimates for the module's ACTIVE state are derived using the CoreMark benchmarking algorithm, a 48 MHz DFLL clock and a 3.3 VDC supply to show a conservative estimation of power consumption. Results are related to CPU activity, clock speed and temperature, which can be optimized further.