3.2.2 Main Configuration and Control

The following figure shows the main block for processor configuration and control.

Figure 3-11. Processor Main Configuration and Control

Table 3-2. Processor Main Configuration and Control
Pin Name	Type	Used for
XIN	Input	Main clock oscillator input
XOUT	Output	Main clock oscillator output
XIN32	Input	Slow clock oscillator input
XOUT32	Output	Slow clock oscillator output
SHDN	Output	Signal used to enable and disable an external power supply circuit
WKUP0	Input	Event detection input pin used to wake up the processor from Shutdown state
JTAGSEL	Input	When pulled high, enables the JTAG boundary scan
NRST	Input	Processor reset input
NRST_OUT	Output	Peripheral reset output
LPM	Output	Low-Power mode enable output
AUDIOCLK	Output	Audio PLL clock output
HHSA_DM	Bidirectional	USB-A negative differential signal
HHSA_DP	Bidirectional	USB-A positive differential signal
HHSRTUNE	Input	USB cell calibration
HHSB_DM	Bidirectional	USB-B negative differential signal
HHSB_DP	Bidirectional	USB-B positive differential signal
HHSC_DM	Bidirectional	USB-C® negative differential signal
HHSC_DP	Bidirectional	USB-C positive differential signal
MIPI_CLK_N	Output	MIPI clock negative differential signal
MIPI_CLK_P	Output	MIPI clock positive differential signal
MIPI_DO_N	Output	MIPI data 0 negative differential signal
MIPI_DO_P	Output	MIPI data 0 positive differential signal
MIPI_D1_N	Output	MIPI data 1 negative differential signal
MIPI_D1_P	Output	MIPI data 1 positive differential signal
MIPI_D2_N	Output	MIPI data 2 negative differential signal
MIPI_D2_P	Output	MIPI data 2 positive differential signal
MIPI_D3_N	Output	MIPI data 3 negative differential signal
MIPI_D3_P	Output	MIPI data 3 positive differential signal
MIPI_REXT	Input	MIPI calibration cell